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LOGIC DESIGN REVISTED

by George Martin

Start ý A Merger ý Make the Design Synchronous ý Toplevel ý Quadlogic ý Counters ý Catch That? ý Sources and PDF

COUNTERS

Figure 3 is the counters schematic, which implements the up/down counting function. The CUP and CDN inputs are converted to EN and DN/*UP. Perhaps I donýt need the AND gate I9, but I put it in as a precaution for safety.

(Click to Enlarge)

Figure 3ýThe counters schematic implements the up/down counting function.

Because I donýt really understand how the counters work, I selected a synchronous 8-bit up/down counter from a library. Perhaps in one array it might be implemented as a fast counter with look-ahead carry. Because most of my designs are cost-sensitive, I chose synchronous counters and, therefore, needed to provide for that timing.

The inputs are presented to counter I11. After one clock, the data outputs of the counter are presented to latch I14, and the count controls (including carry) are presented to counter I17. All of this takes one clock time. So, I need the counter to be stable in 40 ns (if 25 MHz is used). The counting controls are sequenced through I11, I17, and I16, and the data is sequenced through I14, I12, and I13. After the first two clocks, the outputs (O[23..0] for a 24-bit position register) are presented for use.

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