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LOGIC DESIGN REVISTED

by George Martin

Start ı A Merger ı Make the Design Synchronous ı Toplevel ı Quadlogic ı Counters ı Catch That? ı Sources and PDF

CATCH THAT?

If youıve been paying attention, you saw that I labeled each register state that I implemented in this design S1, S2, Q1, C1, C2, and C3. Thatıs six in total. So, a change at the input will take six clocks to be completely visible at the output.

Is 6 ı 40 ns too long for your design? Well, Iım not sure all six are needed, and 40 ns is slow for todayıs logic. But, you need to determine just which states you need and how fast your clock should operate.

Iıve left off features like loading and clearing the counter. Also, I havenıt simulated this design, so donıt just copy it blindly! Or if you do copy it, good luck and let me know how you did!

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