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VOICE RECGNITION CONTROLLED SAILBOAT

Speech-Recognition Control Aids Disabled Sailor

by Mike Smith, Todd Turner, and Steve Alvey

Start ý The Hardware ý Hardware Interface to the SHARC ý Configuring the DSP for UART Access ý Test Run ý Sources and PDF

HARDWARE INTERFACE TO THE SHARC

Figure 2ýThe 48-bit SHARC external port handles a variety of data and instruction formats. Transmission of 8-bit data requires special positioning of the device on the SHARC data bus.

Interfacing between a UART and a DSP bus involves interesting contradictions. Although the UART sends and receives 9-bit data, the device has an external 8-bit wide data port. The ADSP-21061 48-bit external port handles a wide range of data formats, including an interface to an 8-bit device, such as a boot EPROM or UART chip (see Figure 2). The timing control signals are given in Figure 3.

Figure 3ýAlthough the data bus of the SHARC external port is unusual, the timing of the control signals is conventional.

The SHARC 21061(donýt forget that SHARC stands for Super Harvard ARChitecture) has 1 MB of internal RAM that can be configured as independent program and data memory. To read and write to an off-chip external memory location, you activate the appropriate memory select (MS) line. When the MS signal is activated, an address is placed on the memory bus and a read (RD) or write (WR) signal is asserted.

This approach differs from other processors, which multiplex READ/WRITE* control signals. Some processors even require additional decoding logic, as there are no external memory-select or chip-enable signals generated directly by the processor.

After the MS and RD or WR signal asserts, the DSP places data on the bus in a write operation (the peripheral does it with a read). To match the slow speed of the external device, wait states can be programmed for the DSP to access a specific memory location. On the 21061, you can control the number of wait states through an external acknowledge signal (ACK), an internally programmed wait-state register, or a combination of the two.

CONNECTING TO THE DUART

The Exar XR-88C681A UART(actually a dual UART or DUART since it has two separate transceiver channels) handles the 9-bit serial transmission to the SeaTalk bus. Figure 4 shows the connections necessary to interface the 88C681 DUART to the 21061 external data port, address, and control signals. Although the *INTR interrupt signal output on the DUART can be programmed to assert a number of events, in this application, it is asserting *INTR on the reception of a character on channel A. This signal activates the DSPýs IRQ0 interrupt service routine to process the character from the DUART.

Figure 4ýHere you can see the necessary connections of the XR-88C681 DUART to the SHARC external data port.

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