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VOICE RECGNITION CONTROLLED SAILBOAT

Speech-Recognition Control Aids Disabled Sailor

by Mike Smith, Todd Turner, and Steve Alvey

Start ę The Hardware ę Hardware Interface to the SHARC ę Configuring the DSP for UART Access ę Test Run ę Sources and PDF

CONFIGURING THE DSP FOR UART ACCESS

The SHARC processor has four external memory selects and three IRQ pins. On the EZ-Kit Lite, memory-select line MS3 and interrupt line IRQ0 are available to manipulate the DUART.

On microcontrollers, like the 68332, manipulating the chip-select lines can get complicated. Each chip-select line is mapped to a block of addresses anywhere in memory space and configured for 8- or 16-bit operations.

Things are a little more wasteful on the 21061. Here you choose between 48-bit access or no access. As a result, you manipulate bits to ensure that the 8-bit value is correctly placed for transmission and to clear unnecessary bits from received values.

There are four external memory banks, which correspond to the memory-select signals, on the SHARC starting with memory bank 0 at address 0x00400000. Memory bank 1 follows memory bank 0, memory bank 2 follows memory bank 1, and so on. Each bank is the same size and can be configured from 8-KB of 32-bit words to 256-MB of words. Although the base address of memory bank 0 is the same, the base address of the following memory banks varies based on the size of the preceding banks.

Only 16 registers are needed to control the UART. We innocently decided to code the setting for the external memory banks to their minimum 8-KB size, which makes the base address of the DUART on memory select line MS3 at 0x00406000. Only address lines A0 to A3 are explicit in the schematic as the line MS3 provides all the additional decoding necessary to specify the memory locations.

What we didnęt realize was that the DSP kernelęs 16550 UART is mapped to memory-select line MS2. Changing the size of the memory banks should have changed the addresses for the 16550 registers, cutting the communications necessary for debugging.

However, somebody at Analog Devices was way ahead of us, and we got lucky! The kernel assumes that the average user code is written by the dim-witted. The kernel accounts for this by recalculating the effective address of the onboard 16550 before every access just in case the user code changes the bank size from the default value.

Because the DUART doesnęt produce an ACK signal suitable for controlling the speed of memory accesses, you use the internal WAIT register to generate the six memory wait states to synchronize the 21061 and DUART

TALKING TO THE DUART

The C program DuartAlive() (see Listing 1) tests the bus connection. It first sets the 21k processor interface for 8-KB memory blocks and six wait states. If the values stored or received from the DUART Interrupt Vector Register (IVR) are the same, the DUART and SHARC are communicating.

Any register in the DUART can be accessed in C by casting a pointer to the address of the register. Because the EZ-SHARC g21k C compiler from Analog Devices treats characters as a 32-bit number, care must be taken to mask out the upper 24 bits when reading the DUART registers.

The registers must be treated as volatile char, which lets the compiler know that the stored char values may be changed by a process outside of the C program. By assigning this, we avoid the problem of the compiler incorrectly replacing multiple reads with a single read when the same memory location is read repeatedly without writes.

Because both mode registers have the same address, the protocol for accessing the DUARTęs mode registers makes Listings 2 and 3 a little confusing. After a read or write of a value to the one-mode register, the DUART automatically switches to allow access to the second-mode register. The function ResetToMODE1( ) ensures that the correct register is accessed.

With the interface tested, the next step is to set up routines to initialize and control the DUART. Listing 2 shows you how to initialize both the 21k interface and the DUART.

Listing 3ęs routine verifies that itęs possible to send commands from the SHARC to the multidrop bus for receipt by the Autohelm. The full protocol for handling bus collisions is not given.

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