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THE CAPTAIN IS BACK

by Tom Cantrell

Start ý Roots ý ý180s Turn ý eZ Way Out ý Captain at the Crossroads ý Sources

ý180s TURN

The on-again, off-again history of the Z80 family echoes the ups and downs of Zilogýs uniquely turbulent history. How many companies do you know that have gone private twice?

In hindsight, troubles can be traced all the way back to the late ý70s when Zilog got trapped between heavyweights Intel and Motorola in the 16-bit wars. The Z80 was left on autopilot and went adrift. Periodically, Zilog would muster up a course correction, but it didnýt help much (e.g., the ill-fated Z800). Ultimately, it got so bad that other companies were getting more Z80 business than Zilog and, in an odd permutation of NIH (Not Invented Here), Zilog actually ended up licensing the design for their better Z80 (the ý180) from Hitachi.

To Zilogýs credit, they have carried on, upgrading the architecture (with the S version of the core) and introducing a number of derivatives. The most recent addition to the family, the Z80S183, pictured in Figure 1, could be considered the analog ý180 since it incorporates an 8-channel, multiplexed by 10-bit A/D converter and a 10-bit D/A converter. The A/D converter offers separate resistor ladders for the chipýs upper and lower five bits, contributing to a speedy 8-µs conversion.

Figure 1ýThe latest member of the ever-growing ý180 family is the ý183, notable for inclusion of 10-bit A/D converter and D/A converter functions.

The original ý180 peripherals are all thereýUARTs, clock-serial I/O, timers, DMAýbut with a number of refinements and enhancements. For instance, the UART now features more versatile baud-rate generators (up to 512 kbps) and 4-byte receive FIFOs, while the DMA controllers are upgraded with a chaining mode for nonstop service.

As well, there are new features like a watchdog timer (WDT) and real-time clock (RTC). The RTC takes advantage of the PLL clock logic that lets the CPU run at high speeds (up to 33 MHz) off a watch crystal (32.768 kHz).

Thereýs also an interesting programmable I/O sequencer (PIOS) that can be set up to offload from the CPU the details of I/O and timing operations. The CPU and PIOS share access to 256 bytes of the on-chip 2-KB SRAM, in which the programmer can detail the nature and timing of various high-speed operations, including digital and analog (both A/D and D/A) I/O and interrupt generation. Subsequently, the PIOS autonomously performs the specified operations without host CPU intervention.

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