|
by Mark Samuels
Start ý A
Choice PIC ý Getting Connected ý Address
Decoding ý The Identify Drive Command
ý Laying the Foundation ý No
Limits ý Sources and PDF
ADDRESS DECODING
The functional procedure to access the
CF card is also easy, after the 116-page CompactFlash Association
Specification is dissected. The most important bit of information
in the specification is the address decoding of the eight control
registers within the controller portion of the card (see Table 1).
Access to the full range of necessary registers can be achieved using
only three address lines, so ýREG and A10ýA3 are hardwired to VCC
and GND, respectively.
|
ýREG
|
A10
|
A9ýA4
|
A3
|
A2
|
A1
|
A0
|
ýOE = 0
|
ýWE = 0
|
|
1
|
0
|
X
|
0
|
0
|
0
|
0
|
Even RD data
|
Even WR data
|
|
1
|
0
|
X
|
0
|
0
|
0
|
1
|
Error
|
Features
|
|
1
|
0
|
X
|
0
|
0
|
1
|
0
|
Sector count
|
Sector count
|
|
1
|
0
|
X
|
0
|
0
|
1
|
1
|
Sector no.
|
Sector no.
|
|
1
|
0
|
X
|
0
|
1
|
0
|
0
|
Cylinder low
|
Cylinder low
|
|
1
|
0
|
X
|
0
|
1
|
0
|
1
|
Cylinder high
|
Cylinder high
|
|
1
|
0
|
X
|
0
|
1
|
1
|
0
|
Select card/head
|
Select card/head
|
|
1
|
0
|
X
|
0
|
1
|
1
|
1
|
Status
|
Command
|
|
1
|
0
|
X
|
1
|
0
|
0
|
0
|
Dup. even RD data
|
Dup. even WR data
|
|
1
|
0
|
X
|
1
|
0
|
0
|
1
|
Dup. odd RD data
|
Dup. odd WR data
|
|
1
|
0
|
X
|
1
|
1
|
0
|
1
|
Dup. error
|
Dup. features
|
|
1
|
0
|
X
|
1
|
1
|
1
|
0
|
Alt status
|
Device Ctl
|
|
1
|
0
|
X
|
1
|
1
|
1
|
1
|
Drive address
|
Reserved
|
|
1
|
1
|
X
|
X
|
X
|
X
|
0
|
Even RD data
|
Even WR data
|
|
1
|
1
|
X
|
X
|
X
|
X
|
1
|
Odd RD data
|
Odd WR data
|
|
Table 1ýHere
you can see the register address decoding. Note that all data
can be accessed using only three address lines.
|
To load one of these registers, the data
sent is placed on the data lines to the card, the 3-bit address of
the desired register is placed on the address lines, and ýWE is strobed
low. Itýs that easy. By loading the various registers with sector
addresses (either in logical block addressing or cylinder/head/sector
addressing) and a command in the command register, commands can be
sent to perform a read, write, or any number of other operations.
The results of these operations most often go through the internal
buffer, and sequential accesses to the data register incrementally
access each byte.
For example, if a card has a sector size
of 512 bytes, a buffer size of 512 bytes, and the appropriate addressing
registers have been loaded followed by a read sector command, the
buffer is then loaded with the contents of that sector. The first
access to the data register (accomplished by putting the address of
the data register on the address bus and strobing ýOE) will read the
first byte in the buffer. The next strobe of ýOE will read the next
byte in the buffer and so on.
The same would be true of a write sector
operation. After the sector location has been loaded into the appropriate
registers and the write sector command has been loaded into the command
register, the first byte to be written is placed on the data bus.
When ýWE is strobed, that byte is written to the first location in
the buffer. The next byte to be written is then placed on the data
bus, ýWE is strobed again, and so on. Because these operations go
through the buffer, which is internally read from and written to a
full sector at a time even if the desire is only to write one byte
to the card, a full 512 bytes must be written to the buffer. The data
in the buffer does not transfer to the card memory until the buffer
is full.
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ýCircuit Cellar, the Magazine for Computer Applications. Posted with
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