Soft Cell

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SOFT CELL

Silicon Online by Tom Cantrell

Start ı Start Making Sense ı Viva La Difference ı No Free Lunch ı Tool Sweet ı Real Time or Hard Time? ı Small Step, Big Journey ı Sources and PDF

VIVA LA DIFFERENCE

Letıs take a look at the latest field-programmable SoC to cross my desk. The ProMic comes from Microlor Systems, which is based in France, bringing an international flavor to the field-programmable SoC fray (see Figure 1).

Figure 1ıThe ProMic from Microlor Systems is a soft-core CPU for FPGAs that can be combined with application-specific soft peripheral logic (such as the UART, I²C, and PWM shown here) in a field-programmable System-on-Chip.

Regarding performance, ProMic is a middle-of-the-road 16-bit machine (see Table 1). It has a simple, clean, general-register architecture and a consensus set of 50 or so instructions that comprise the essence of RISC theology, with a few extras such as bit manipulation and auto-increment/decrement thrown in.

	PIC16 @ 10 MHz	ST 72 @ 16 MHz	ProMic 8 @ 10 MHz	ProMic 16 @ 10 MHz
char	169	57	72		Search of 1 byte in an array of 40
bubble	1504	857	174	132	Bubble sort of 10 words of 16 bits
16mul	72	18	41	29	16 ı 16 bits unsigned multiplication
32div	248	222	54	36	Division of a 32-bit word by 16 bits
shright	13	10	6	4	Five ranks right shift in a 16-bit word
btsrt	72	62	39		Set, reset, and test of 3 bits in an array
string	741	282	395		Search a 16-byte string in an array
blkmov	308	121	17		Search a 16-byte string in 128 characters
convert	512	241	112		Change an 80-byte array format
Total	3639	1870	910
Ratio	3.99	2.05	1
Execution time in microseconds. Table 1ıIts single clock per instruction throughput gives ProMic a performance advantage over traditional MCUs.

ProMic relies on a five-stage pipeline (see Figure 2), and most instructions execute in a single cycle. The only exception is taken branches, which require four cycles. As a Harvard design, ProMic accesses separate instruction and data memories. Note that ProMic uses a dedicated hardware stack (for call and interrupt return addresses) that is not accessible to software. Of course, for parameter passing, a general-purpose register can be used as a software stack pointer, thereby accessing the normal data memory. Clock rates are competitive, ranging from 20 to 50 MHz depending on the targeted FPGA device.

Figure 2ıProMic requires a five-stage pipeline (aggressive for a mid-range controller) to deliver double-digit clock rates. (Click to enlarge)

That brings us to the issue of portability, which perhaps is the most notable feature of ProMic. The generic VHDL design, compatible with the popular synthesis tool suite from Synplicity, not only runs on a variety of FPGAs from Xilinx, Altera, and Actel but could easily be moved to an ASIC as well.

As for price, the ProMic story is blessedly simple: no complicated or invasive royalty schemes, no semantic parsing of what constitutes a particular project or location, and no expensive and time-consuming letıs-make-a-deal negotiations.

The VHDL source and an unlimited license goes for 39,990 Euros, and last I looked, it was 1.12 Euros to the dollar. Feel free to use it in different projects on a variety of FPGAs and ship as many units as you want without worrying about royalties.

Thatıs a decent but nontrivial price. Donıt forget that youıll need an entire FPGA synthesis tool chain as well. Alternatively, you can opt for an object-only (EDIF) copy of a specific ProMic implementation on a particular FPGA for only 4990 Euros. Follow up your first order with a different implementation (1990 Euros) or one ported to a different FPGA (490 Euros), and it costs even less.

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