architecture FA of Full_Adder is
component Half_Adder
port
(W,X: in bit;
Y,Z : out bit);
end component;
signal Y0,Z0,Z1 : bit;
begin
HA0: Half_Adder port map (AI, BI, Y0, Z0);
HA1: Half_Adder port map (CYI, Y0, SUM, Z1);
CYO <= Z0 or Z1;
end FA;

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