entity RIP4 is
port 
(A,B : in bit_vector(3 downto 0);
CI: in bit;
S : out bit_vector(3 downto 0);
CO : out bit);
end RIP4;
architecture RIPADD of RIP4 is
-- Specify the Full Adder subcircuit
component Full_Adder
port
(AI,BI,CYI: in bit;
SUM,CYO : out bit);
end component;
-- Reserve a few signals for internal connections
signal CY0, CY1, CY2 : bit;
begin
FA0: Full_Adder port map (A(0), B(0), CI, S(0), CY0);
FA1: Full_Adder port map (A(1), B(1), CY0, S(1), CY1);
FA2: Full_Adder port map (A(2), B(2), CY1, S(2), CY2);
FA3: Full_Adder port map (A(3), B(3), CY2, S(3), CO);
end RIPADD;
entity Full_Adder is
port
(AI,BI,CYI: in bit;
SUM,CYO : out bit);
end Full_Adder;
architecture FA of Full_Adder is
component Half_Adder
port
(W,X: in bit;
Y,Z : out bit);
end component;
signal Y0,Z0,Z1 : bit;
begin
HA0: Half_Adder port map (AI, BI, Y0, Z0);
HA1: Half_Adder port map (CYI, Y0, SUM, Z1);
CYO <= Z0 or Z1;
end FA;
entity Half_Adder is
port
(W,X: in bit;
Y,Z : out bit);
end Half_Adder;
architecture HA of Half_Adder is
begin
Y <= W xor X;	-- This is the sum bit
Z <= W and X;	-- This is the carry bit
end HA;

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