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AN INTRODUCTION TO VHDL

Designing Hardware with Software

by James Antonakos

Start ý Levels of Design ý The Interface ý The Body ý Full_Adder ý Half _Adder ý Identifiers, Data Types, and Operators ý Examples ý The Five-Input AND Gate ý The 2:4 Decoder ý Timing Examples ý Other Methods ý Sources and PDF

THE 2:4 DECODER

The design entity for a 2:4 decoder is shown in Listing 13. Note the use of an enable input (ENbar), which is set up as an active-low enable. When ENbar is low, the selected output of the decoder will go low. If ENbar is high, all outputs remain high.

USING PACKAGES

Packages are holding places for design entities that are frequently used. For example, after the 4-bit ripple adder is working, you may want to place it in a package so that it can be easily accessed by the VHDL compiler at a later time. Packages are stored in libraries, which are then imported into your design using a simple statement, use MYLIB.RIP4.all;. Here, the RIP4 package within the MYLIB library is made available to all the entities in the design.

There are several packages that contain useful data types, input/output operations, logic definitions, and many other entities. These packages are called STANDARD, STD_LOGIC, and TEXTIO. One package, called STD_LOGIC_1164 (located in the IEEE library), contains a definition for a nine-value logic system popular with most designers. The nine values are U (uninitialized), X (forcing unknown), 0 (forcing zero), 1 (forcing one), Z (high impedance), W (weak unknown), L (weak low), H (weak high), and ý (donýt care).

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