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AN INTRODUCTION TO VHDL

Designing Hardware with Software

by James Antonakos

Start ý Levels of Design ý The Interface ý The Body ý Full_Adder ý Half _Adder ý Identifiers, Data Types, and Operators ý Examples ý The Five-Input AND Gate ý The 2:4 Decoder ý Timing Examples ý Other Methods ý Sources and PDF

TIMING EXAMPLES

As always, time can be your friend or your enemy in a digital circuit. For applications that have critical time requirements or for those that wish to simulate a digital circuit down to the femtosecond, VHDL provides the necessary timing features. One way to specify the delay of a logic operation is to indicate its time directly in the body (see Listing 14).

Here, the delays of the XOR gate and the AND gate are fixed at 5 ns. Figure 8 shows a simplified timing diagram illustrating the effect of gate delay in a two-input gate. Table 2 shows the units of time available in VHDL.

Figure 8ýThe gate delay between the input and output can be seen here.

VHDL provides an inertial delay model that essentially eliminates the effects of short-duration logic level changes. For example, a gate with a delay of 8 ns may experience a high-level pulse for 3 ns. The inertial delay model ignores the 3 ns pulse because it is less than the propagation delay.

Getting back to the five-input AND gate design entity covered previously, which design do you prefer now?

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