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AN INTRODUCTION TO VHDL

Designing Hardware with Software

by James Antonakos

Start ý Levels of Design ý The Interface ý The Body ý Full_Adder ý Half _Adder ý Identifiers, Data Types, and Operators ý Examples ý The Five-Input AND Gate ý The 2:4 Decoder ý Timing Examples ý Other Methods ý Sources and PDF

THE INTERFACE

Design entities, which contain an interface and a body, are the objects used to specify what hardware components are used and how they are connected. The interface describes the number and type of signals used by the entity, and the body describes how the signals are connected and related.

The interface for the 4-bit ripple adder is shown in Figure 3. The name of the entity is RIP4. The 4-bit ripple adder adds two groups of four bits together (plus a carry input bit, CI) and generates a 4-bit sum and a carry output bit (CO). Inputs and outputs to the entity are identified by the port keyword. A port can be an input, output, or bidirectional signal. The A and B inputs to RIP4 are specified as 4-bit vectors, groups of bits that share common properties. The "3 downto 0" portion of the statement indicates that four input bits are needed for A and B, numbered 3, 2, 1, and 0, from left to right. Bit 3 is the MSB and bit 0 is the LSB. In other areas of the VHDL specification, these bits are referred to as A(0) through A(3) and B(0) through B(3). Note that there is nothing in the entity interface to indicate how the ripple adder does its job. This is left for the second part of the design entity, the body portion.

Figure 3ýThe ripple adder design entity interface and diagram can be seen here.

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