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AN INTRODUCTION TO VHDL

Designing Hardware with Software

by James Antonakos

Start ý Levels of Design ý The Interface ý The Body ý Full_Adder ý Half _Adder ý Identifiers, Data Types, and Operators ý Examples ý The Five-Input AND Gate ý The 2:4 Decoder ý Timing Examples ý Other Methods ý Sources and PDF

THE BODY

The body portion of a design entity describes how the function of the entity is performed. In Figure 2, you can see how the first expansion of the ripple adder indicates that it contains four full adder (FA) blocks. These are the components of the ripple adder. The body portion of the RIP4 design entity is responsible for specifying the number and type of components used by the entity (see Listing 1).

Refer to Figure 4 and the body statements as I discuss the individual pieces of RIPADD. The component portion of RIPADD indicates that the Full_Adder design entity will be used to implement the ripple adder. The port information of the Full_Adder entity is required to make the necessary connections indicated by Figure 4.

Figure 4ýHere you can see the full adder connections in the ripple adder.

The signal keyword is used to define internal signals that allow the four full adders to be cascaded by connecting the carry output signals (CYO) to the carry inputs (CYI).

As expected in an object-oriented environment, you are able to reuse the single Full_Adder component by instantiating four copies of it (FA0 through FA3). Each copy is instantiated differently in the four port-mapping statements, with actual signal names being substituted for the desired input/output connections.

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