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AN INTRODUCTION TO VHDL

Designing Hardware with Software

by James Antonakos

Start ý Levels of Design ý The Interface ý The Body ý Full_Adder ý Half _Adder ý Identifiers, Data Types, and Operators ý Examples ý The Five-Input AND Gate ý The 2:4 Decoder ý Timing Examples ý Other Methods ý Sources and PDF

HALF_ADDER

The last piece of the design is the Half_Adder entity (see Figure 6), which is instantiated twice in each Full_Adder entity, for a total of eight times. The interface and body of the half adder are shown in Listing 4. Again, signal assignment statements are used to generate the required logic function.

Figure 6ýAn XOR gate and an AND gate are used to make a half adder.

Bear in mind that the focus of this design is to implement a 4-bit ripple adder using VHDL. You may have many questions about how the half adder works, or why the OR gate is required in the full adder, or why I did not start with the half adder and work my way up. The first two questions can be answered by reviewing your digital textbook. The third question almost answers itself during a design. With experience, you will discover that adding layer after layer of detail is a natural process, after the big picture is known.

PUTTING IT ALL TOGETHER

All of the design entities for the 4-bit ripple adder are shown in Listing 5. At this point, I should pause to review what has been accomplished. The design began with a high-level specification of a 4-bit ripple adder, the RIP4 entity. Then, in line with the nature of top-down design, the next level of the design was detailed, showing how the Full_Adder entity (used as a component in RIP4) was designed. Then the Half_Adder component of the Full_Adder entity was described as well, completing the design.

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