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AN INTRODUCTION TO VHDL

Designing Hardware with Software

by James Antonakos

Start ý Levels of Design ý The Interface ý The Body ý Full_Adder ý Half _Adder ý Identifiers, Data Types, and Operators ý Examples ý The Five-Input AND Gate ý The 2:4 Decoder ý Timing Examples ý Other Methods ý Sources and PDF

THE FIVE-INPUT AND GATE

By definition, the logical operators in VHDL are limited to two inputs (with the exception of the inverter). What do you do if we need a five input AND gate? First, letýs specify the interface (see Listing 9).

Here you can see the five inputs (A through E). How should they be reduced to a single output? The first technique can be seen in Listing 10.

Take a moment to sketch the schematic of the AND5 circuit. Does it look like it will work? When you are finished, do the same for this architecture body (see Listing 11).

Can you think of any advantages or disadvantages of one specification over the other? Is there any reason why you should stay away from the following third solution (see Listing 12)?

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