During the last few years, the industry has witnessed the introduction of several, incredibly fast DSP and RISC processors with remarkable benchmarks for popular algorithms and sophisticated hardware engines for caching, data movement, and addressing.

For example, Analog Devicesę new 21160 Hammerhead processor operates at a clock frequency of 100 MHz and executes six floating point instructions every 10-ns clock cycle, resulting in 600 Mflops of peak horsepower. Its 48-bit external data bus can move six bytes every 15 ns for an I/O peak transfer rate of 528 Mbps.

Even though not truly a DSP, the popular Motorola PowerPC MPC-750 (running at a 400- MHz clock rate) delivers 733 MIPS and 400 Mflops. Using its external 64-bit data bus, it can handle peak I/O rates to peripherals at over 1000 Mbps.

The recently introduced Texas Instruments TMS320C6203 DSP executes eight 32-bit instructions in parallel within a 3.33-ns instruction cycle time, yielding 2400 MIPS operation. An on-chip multiple-path ALU and four-channel DMA controller are coupled to support extremely high-speed I/O peripherals. With dual 32-bit parallel data busses, it can move data to I/O devices at a combined rate of 1800 Mbps!

Now, consider typical board-level product offerings containing four, six, or even eight of these devices on a single board. Data transfers in and out of these boards to the fast communication links (such as, RACEway, FPDP, fiber channel, and high-speed peripherals like wideband A/D converters), seriously challenging traditional I/O structures and pointing out the need for a better solution.