VIM: A POWERFUL NEW MEZZANINE

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VIM: A POWERFUL NEW MEZZANINE

Lessons from the Trenches by Rodger Hosking

Start ı Design Rationale ı VIM Streaming Parallel Bus ı Serial Ports ı Power Supply ı Single-Slot VIM-Based Systems ı Sources and PDF

SERIAL PORTS

The VIM serial interface supports two full-duplex channels, each with two data lines, three clock lines, and two framing signals. These seven signals provide an extremely flexible and configurable interface to many different types of serial devices. Table 2 shows each of the lines with the direction shown relative to the mezzanine module.

Signal	Lines	Direction	Description
Receive data	2	Out	One line for each of two serial ports
Receive clock	2	In/Out	One line for each of two serial ports
Receive frame sync	2	Out	One line for each of two serial ports
Transmit data	2	In	One line for each of two serial ports
Transmit clock	2	In/Out	One line for each of two serial ports
Transmit frame sync	2	Out	One line for each of two serial ports
External clock	2	Out	One line for each of two serial ports
Table 2ıSignals associated with the serial ports provide a flexible and configurable interface to many serial devices.

The receive and transmit clock lines can be configured under software to support peripherals, which must either receive or supply clocks. An external clock signal may be applied to replace the processorıs serial clock timing reference.

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Many of the new processors feature integral serial ports, often with sophisticated framing and TDM hardware conveniently linked to DMA controller signals. This nicely supports serial streams from digital telecom interfaces like T1/E1 and matches the processing functions of the telecom-oriented DSPs like the ıC6203 which can handle a full T1 span of V.90 modems.

RANDOM ACCESS CONTROL/STATUS INTERFACE

Control of the interfaces and circuitry on the mezzanine module is accommodated with the VIM random access control/status bus, which closely resembles a generic microprocessor interface. This allows registers and other programmable resources on the module to be mapped into a conveniently located read/write address region of the processor memory space.

Signals present on this portion of the VIM interface are shown in Table 3. The names of most of the lines are self-explanatory, and the direction shown is with respect to the VIM module.

Signal	Lines	Direction	Description
Data bus	32	In/Out	Bidirectional data bus (buffered to processor)
Address bus	16	In	Address lines (subset of processor address)
Output enable	1	In	Enables the module to drive data bus
Read strobe	1	In	Read control signal
Write enable	1	In	Write control signal
Ready output	1	Out	Data transfer complete acknowledge
Reset	1	In	Resets or initializes the module
Clock input	1	In	Processor related clock
Interrupt output	1	Out	Interrupt to the processor
Module present output	1	Out	Indicates that a module is installed
Table 3ıSignals present on the control/status interface allow registers and other programmable module resources to be mapped into the processor memory space.

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