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DESIGNING WITH VHDL

by Ingo Cyliax

Start ę The Benefits ę Learning the Language ę Signal Types ę Mathematical Operations ę Sources and PDF

I was going to write about using ASMs to design digital logic for FPGAs, however, I thought I would digress a little and write about using VHDL for digital design. What prompted me was Xilinxęs release of a free version of its design environment for download from the company web site. Itęs called WebPack and is a version of Xilinx's Foundation 3.2i software environment, but it is limited to only a few architectures. Why am I talking about VHDL? Well, it seems like hardware description languages (HDL) such as VHDL and Verilog are becoming the mainstream design entry mechanism for designing FPGAs and CPLDs. The release of WebPack somewhat illustrates this because itęs becoming obvious that you have to use HDLs.

Most of the comments I make here really apply to both Verilog and VHDL, but I will use VHDL as my main example to illustrate some of the techniques. VHDL is perhaps the harder of the two languages to learn and is not as popular in many U.S. companies as Verilog. But, itęs widely used in Europe and is the preferred choice by the DOD and NASA. To many programmers, VHDL looks arcane, and Verilog looks more C-like. However, both are just as adequate at expressing digital logic, and most logic compilers will understand both languages. They convert both VHDL and Verilog into an internal representation first and then go from there.

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