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DESIGNING WITH VHDL

by Ingo Cyliax

Start ý The Benefits ý Learning the Language ý Signal Types ý Mathematical Operations ý Sources and PDF

SIGNAL TYPES

VHDL has several signal types. This is necessary because you want to be able to differentiate between signed and unsigned arithmetic. The type of signals available depends on the type of package you include. Table 1 shows what types you need to use with specific packages to use unsigned or signed arithmetic.

Of course, normal signals of std_logic are only 1 bit long and donýt really need types.

Inferring muxes can also seem like a black art. In FPGAs, there are many kinds of muxes you can use. Listings 3 a, b, c, and d show the different styles. The first style seen in Listing 3a is implemented using if/elseif statements. This style of mux is sometimes hard to read, and realize that the compiler will actually infer a mux from it. A better method is to use the code in Listing 3b. Here the mux is implemented using a case statement. In Listing 3c, the mux is implemented using tristate buffers. This style of mux is efficient in FPGAs that support internal tristate buffers, and the number of mux states is big. Finally, in Listing 3d, you can see that itýs similar to the style in Listing 3a, but in this case, no mux is inferred because there is no final else clause.

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