The eZ80 Webserver

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The eZ80 Webserver

Technically Speaking An 8-Bit CPU Takes on the Internet

by James Antonakos

Start ı Software Model ı Memory Map ı Instruction Set ı On-Chip Peripheral Registers ı Hardware Architecture ı TCP/IP Stack Operation ı eZ80 Evaluation Board ı Connecting the System ı Developing the Hardware and Software ı Application: A Web-Based Security System ı Other Applications ı Win Your Own! ı Sources and PDF

DEVELOPING THE HARDWARE AND SOFTWARE

Hardware interfacing with the evaluation board is accomplished through the use of two 60-pin connectors. Table 4 illustrates the types of signals available on each connector.

Connector	Signals
Memory	Address bus, data bus, control and interrupt signals, programmable chip-selects, power, and ground
General-purpose I/O	PA, PB, PC, and PD I/O ports, power, and ground
Table 4ıDetails of the two expansion connectors on the evaluation board are listed here.

Programming the evaluation board is accomplished with the Zilog development system shown in Photo 2. Support for C and assembly language is provided as well as in-circuit emulation.

(click here to enlarge)

Photo 2ıC programs are easily compiled into eZ80 machine language and downloaded into the evaluation board for execution.

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