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An 8-Bit CPU Takes on the Internet
by James Antonakos
Start ý Software
Model ý Memory Map ý Instruction
Set ý On-Chip Peripheral Registers
ý Hardware Architecture ý TCP/IP
Stack Operation ý eZ80 Evaluation Board
ý Connecting the System ý Developing
the Hardware and Software ý Application:
A Web-Based Security System ý Other Applications
ý Win Your Own! ý Sources
and PDF
ON-CHIP PERIPHERAL REGISTERS
Accessing the on-chip peripherals is
done through the use of internal registers mapped to various I/O port
addresses. Any I/O operation to a port in the range of ports shown
in Table 2 accesses the on-chip register. I/O operations to port addresses
between 00 and 7F cause the external I/O signals to activate.
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Address (hex)
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Register category
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80ý91
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Programmable reload/counter timers
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93ý95
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Watchdog timer
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96ýA5
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General-purpose I/O ports
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A8ýB3
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Chip select/wait state generator
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B4ýB5
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On-chip RAM control
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B6ýDF
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Universal Zilog interface blocks
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E0ýED
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Multiply accumulator
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EEýFF
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DMA controllers
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Table 2ýEach
on-chip peripheral is controlled by multiple registers.
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