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VIRTEX PROTO BOARD

by Ingo Cyliax

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I originally planned to follow my last piece with an article about how to design with multipliers. Well, to shorten the story, the software I intended to use in designing some of the multiplier examples didnıt work.

The longer version of the story is that, because I was working on a project, I needed to upgrade my FPGA design software to the latest and greatest version. Of course, because it runs under Windows, this doesnıt always work the way you think it will. Such was the case with the new installation, so I decided to downgrade to the original version. Unfortunately, it doesnıt work at all now. At this point, I needed to uninstall both versions by removing all traces of .dlls, executables, environment variables, and registry entries, or just resort to reinstalling Windows. Iım sure youıve been there at one time or another. Someday theyıll bring out these design tools under Linux. At least I can dream.

My design environment under Windows is a mess, but the Linux environment on my laptop still works well, enabling me to write this article. This month, Iıll talk about the Virtex prototyping board Iım using for the project that got me in troubleıthe Virtual Workbench 300 (VW-300) from the Virtual Computer Corporation (VCC).

THE BOARD

The board is a prototyping board for the Xilinx Virtex series FPGA. Virtex is Xilinxıs high-end FPGA, boasting densities of up to one million gates (more in the Virtex-E). Remind me to write a piece about how to compute realistic gate densities in FPGAs that actually mean something.

Virtex has some nice architectural features that make it suitable for large system-on-a-chip designs that include 32-bit processor cores, peripherals, and high-performance digital signal processing. There are several types of memory from SelectRAM that can be used for small register files (i.e., BlockRAM), which are large 4-Kb RAM modules available on-chip. BlockRAMs are highly flexible because they can be configured as either single- or dual-ported memory with either 1 or 16-bit wide ports. Other than that, they are of the look-up table-based CLB architecture, with plenty of routing resources to connect them with fast carry support between adjacent CLBs.

The I/O on Virtex chips is perhaps the best feature. There are several banks of I/O, each bank powered by its own I/O power supply and input reference voltage. With the appropriate power supplies, various signaling standards can be implemented. Table 1 shows the supported types.

Of course, the inputs are also 5-V tolerant if itıs selected and have programmable pull up/pull down and weak keepers.

To make interfacing even easier, Virtex has several delay locked loops (DLL). These can be used to match internal clock signals to external clocks in order to reduce the effects of on/off chip latencies at high clock rates.

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