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VIRTEX PROTO BOARD

by Ingo Cyliax

Start ý No Re-flow Oven? ý More Options ý Upon Arrival ý Sources and PDF

NO RE-FLOW OVEN?

Virtex FPGAs are available in BGA packages. BGA packages are the package of choice for large chips these days. Of course, like many new package styles, they are harder to mount when prototyping or building one-offs. BGAs have small solder balls on the bottom of the chip that match up with small solder pads on the PCB. The BGAs are placed on the PCB and then need to be heated in an oven for the solder balls to melt and bond with the solder pads. Of course everyone has a re-flow oven these days.

Because I donýt have a re-flow oven handy and didnýt have enough time to track down a facility that could handle mounting these packages, I had to buy a prototype board for this project. The project, incidentally, was demonstrating a 32-bit processor core I developed for my day job. I needed a Virtex board with a large enough chip and some external memory pre-wired, along with a prototyping area for all the extra stuff.

After searching Optimagicýs web site, which is great for FPGA resources, I found that the VW-300 fit the bill, so I ordered one.

Besides the Virtex chip, the VW-300 has a lot of memory, a clock, and connector resources. In addition, there are LEDs, switches, push buttons, 8-digit alphanumeric LED display, and other neat stuff all on an 5.5ý ý 5.5ý board (see Photo 1).

Photo 1ýLook at all this neat stuff on such a small board!

There are three memories on the VW-300. A 256K ý 8-bit flash memory is used to store startup configuration for the FPGA. From the factory, it has a demo that scrolls continual advertising over the alphanumeric display. Itýs nice to have something running so you can make sure everything is OK (after youýve taken it out of the box and built a power supply). The flash memory can be reprogrammed by removing it from its socket (itýs PLCC footprint flash memory) and programming in a programmer. A CPLD is used to interface the flash memory to the Virtex part to perform Xilinxýs SelectMAP partial reconfiguration protocol. Because the CPLD is flash memory-based, I suppose it could be reprogrammed to perform other functions.

BURST MODE

Besides the flash memory, the VW-300 also has a 256K ý 18-bit synchronous burst mode fast static RAM (SBRAM). This is a memory module normally used for off-chip L2 processor cache and supports burst mode operations. The cycle time of the memory installed is 6 ns (166 MHz), which means it can transfer at a peak rate of over 332 MBps. Because the SRAM is fast but not too large, an 80-ns 1M x 16 x 4 SDRAM is also included onboard.

The SRAM and DRAM memories are devices attached to the FPGA. By itself, the Virtex does nothing special with the memories. You would have to design in a SRAM or DRAM controller into the design loaded on the FPGA in order to use the memory. In this project, you can use the SDRAM as traditional program and data memory, and the SRAM as fast buffer memory or cache memory. The Xilinx web site has cores that can be used to control burst mode SRAM and SDRAM in a Virtex design.

Because the Virtex also has on-chip memory block and small look-up table-based register files, you can use a full spectrum of memory hierarchyýfrom small single- and dual-ported register files (SelectRAM) running at sub-nanosecond access times, to larger memory block (BLOCKRAM) running at less than 5-ns access times. To get to off-chip memory, you have to figure the latency it takes to get in and out of the chip and protocol issues, in addition to the access times of the memory.

For example, to access SBRAM you have to send the address and wait for the data to burst out of the memory sequentially. Although the peak burst rate is fast at 166 MHz, the total access time to get four words is at least five cycles. Figure 1 shows timing diagrams for SBRAM access. In contrast, BlockRAM works as true random access memory, not in burst mode. In any case, with this board you have all the options covered.

Figure 1ýHere you can see the timing diagrams for SBRAM access.

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