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DESIGN DOWNLOADING AND DEBUGGING

by Ingo Cyliax

Start ý SRAM-based FPGAs ý Debugging ý Sources and PDF

Last month, I showed you how to use the software needed to design FPGAs or CPLDs. I used a simple design to illustrate that you can use a familiar schematics editor, using familiar libraries of gates.

The design from last month was a simple bi-colored LED blinker that I frequently use to test my design environment and initial hardware designs. The project featured a simple 4-bit counter that prescaled an internal oscillator, which can be found in a Xilinx XC4000 series part. Before the part is initialized, the dedicated output "high during configuration" (HDC) and "low during configuration" (LDC) will turn the LED red, while the flasher will blink it green.

While not all FPGAs and CPLDs have an onboard RC oscillator, it can be adapted. For example, instead of flashing the bi-colored LED, it could just turn an LED on. This way, you can tell the difference between a properly configured device and a device that is not configured.

This time, I want to go through the steps necessary to get the design from last month into an actual part. In later installments, I'll cover more interesting designs than a flasher, I promise.

FLASH-BASED CPLDs

As I have mentioned before, these programmable devices come in two basic flavors, CPLDs and FPGAs. These days, most CPLDs are flash-memory based parts. Meaning, you can program and re-program them, and then keep using them once they have been programmed. These devices are non-volatile.

Flash-based CPLDs are typically programmed in circuit. You populate your design with unprogrammed parts and then program the CPLD (and other flash memory parts) before you use it the first time. That is why most CPLDs use the JTAG port for programming. JTAG is a serial bus that daisy chains all JTAG-based devices on a PCB or system. JTAG allows you to look at all of the I/O pins of a JTAG-based device in order to do boundary scan testing.

A JTAG tester can then test all of the connections on your circuit board and, finally, be used to program the device on the board for the final testing phase. However, JTAG testing and how the protocol works is not what I want to cover here.

When youýre starting out, you'll probably be dealing with one CPLD that youýll want to program. It might be on a prototype board, but it's still programmed via the JTAG port. If you look at the datasheet for the particular CPLD you are going to use, you will find the JTAG pins. These have standard names like:

ý TDI: test data in
ý TDO: test data out
ý TCK: test clock
ý TMS: test mode

JTAG uses the TCK signal to shift data into the TDI port and shifts it out of the device using the TDO port. The TMS signal is used to tell the JTAG controller on the chip to either listen or bypass. Figure 1 shows a CPLD system with programming interface.

Figure 1ýA simple CPLD design, which is programmed via the JTAG interface. All you need is power and the JTAG signals (TDI, TDO, TCK, and TMS).

CPLD vendors provide JTAG programming dongles, which are usually included in the software package. Simple, parallel-port-based JTAG dongles are also described in some datasheets and online documents if you want to build your own.

Xilinx has their own version of the dongle. In fact, they have two different versions. Xilinx has the Xchecker III parallel cable and the serial Xchecker cable. Of the two, the serial Xchecker cable is more capable when you need to program and debug SRAM-based FPGAs. (More about those later.) The parallel cable is described in the on-line manual.

Programming is simple. You hook up the dongle to the JTAG pins in your design. At this point, it helps to add some 0.1" headers for the JTAG signals. You also need to wire V_CC and GND to the Xilinx Xchecker, mostly to power the circuitry in the Xchecker, but also to detect if there is a device attached to it.

Once you are connected and the design has been compiled for the particular chip, click on the box labeled "Program Hardware" in Foundation and select JTAG programmer. This brings up the JTAG programming utility. It gives you a worksheet where you can allocate different designs to different CPLDs in your JTAG chain, but if you're only using one part, itýs ready to go. Program the device, disconnect the cable, and you're done. From now on, each time you power up your circuit, the CPLD will come up with the design you programmed into it.

There are variations of this scheme. For example, if you have a processor in your system, you can use it to control the JTAG port and program the CPLDs the first time around, or later when you want to update the design. Because CPLDs have a complete JTAG controller on-chip, they can be used to test your circuit board connections. You need to make sure the CPLD is wired to the parts of the board you want to test, and use a JTAG tester. (By the way, Xilinx also has a Java-based JTAG application you can use to do more sophisticated JTAG testing and programming.)

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