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ANALOG PLD ANYONE?

by Tom Cantrell

Start ı Viva la Differential ı Virtual Prototype ı Sources and PDF

VIVA LA DIFFERENTIAL

The programmable analog circuit (PAC) chips from Lattice integrate the links in the chain between sensor and A/D, also known as the Analog Front End (AFE), onto a single chip.

The PAC10 (see Figure 2) includes four cells, which Lattice calls PAC blocks, each comprised of two instrumentation amps and a summing output amp surrounding an analog routing area (programmable interconnect). Centralized functions include a precision 2.5-V reference, auto-calibration mechanism, JTAG interface, and non-volatile EEPROM configuration memory. The configuration memory is in-system programmed via JTAG.

Figure 2ıThe Lattice ispPAC10 integrates four PAC blocks, each comprised of two instrumentation amps and an op-amp, with the various parameters (gain, feedback capacitor value, etc.) and interconnection defined by EEPROM configuration memory.

Each cell supports a variety of configurations. The instrumentation amps feature programmable gain (ı1, 2, 3ı10) and polarity, while the output amp has a switchable (on/off) feedback resistor and a pool of 128 capacitors covering a range from about 1 to 63 pF.

Auto calibration, which trims input offset to a guaranteed 1 mV, is automatic on power-up. It can also be invoked at runtime using the CAL pin or via JTAG. Together, the automatic and invocable calibration help compensate for both long-term (aging) and short-term (temperature) drift. In addition to the automatic power-up calibration, the datasheet recommends a calibration after the chip temperature stabilizes, and at least once every 24 hours after that.

The PAC20 (see Figure 3) combines two of the cells with two comparators and an 8-bit DAC. Furthermore, 1.5- and 3-V references are provided in addition to the standard 2.5-V reference. Embellishments include a pin-selectable multiplexer fronting one of the instrumentation amps and pin-selectable polarity for another.

Figure 3ıThe ispPAC20 mixes and matches two of the PAC blocks with a pair of voltage comparators and an 8-bit DAC.

Comparator connections can be either internal or external, and the output of one comparator can be clocked in a register or XORed with the other comparator output to establish a window function, typically exploiting the DAC for a programmable threshold. One of the app notes on the Lattice web site ("Using the ispPAC20 for Temperature Monitoring") demonstrates using the DAC to vary the threshold in 23.4-mV steps to achieve 1ıC accuracy using a 2N2222A transistor. This application also exploits the optional hysteresis for the comparators to avoid excessive jitter (on/off cycling) around the setpoint.

The combination of amps, gain, and capacitors is well suited for classic active filter. The instrumentation amps exhibit high input impedance (10⁹ ohms), so they wonıt load even the weakest sensor while the differential inputs reject common mode noise.

Input range is 1 to 4 V, and the differential path continues through the output amp all the way to the pins, thus doubling the effective output swing to 6 V_p-p (at a robust 10 mA). Nevertheless, itıs not hard to put PACs to work in single-ended applications using the on-chip 2.5-V reference as a bias generator. The differential output bias also defaults to 2.5 V but can alternatively be set by a pin (CMV, Common Mode Voltage).

The PACs are optimized for 10- to 100-kHz applications, although higher bandwidth is possible if gain is limited. Specs are goodıat 100 kHz, Common Mode Rejection (CMR) is 55 dB, Total Harmonic Distortion (THD) is ı62 dB, and the Signal to Noise (S/N) ratio is a healthy 103 dB.

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