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SOFTWARE IMPLEMENTATION OF I²C PROTOCOL

by Dariusz Caban

Start ý The Bus ý The Protocol ý The Process ý Conclusions ý Sources and PDF

THE BUS

The I²C interface is modest in its hardware resource requirements, because only a single pair of signal lines is needed: serial data (SDA) and serial clock (SCL) (see Figure 1). Both lines are bidirectional and must be connected to a positive supply voltage via pull-up resistors. The SDA and SCL pins of each device also must have an open drain or open collector in order to perform the wired AND function. Data can be transferred at a rate of up to 100 kbps in Standard mode, up to 400 kbps in Fast mode, and up to 3.4 Mbps in High-Speed mode. Each slave on the bus is identified by a unique address.

In Standard mode, 7-bit addressing is used. In other modes, slaves can have 7- or 10-bit addresses. The number of devices that can be connected to the same bus is limited by the maximum bus capacitance of 400 pF.

The I²C bus can be controlled by more than one master. If two or more masters simultaneously initiate data transfer, collision is detected and an arbitration procedure is performed. The arbitration doesnýt cause data corruption, however, most system designs include only one master.

Only the master generates the clock, but transmission speed can be adjusted to the internal operating rate of the addressed slave. This adjustment is made by clock stretching, in which the slave keeps the SCL pulled low until it is ready to continue.

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