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MONITORING YOUR MICRO

by Daniel Mann & Jim Magro

Start ý Data Gathering ý DRAM Memory Interface Buffer ý Write Buffer "Hit" Monitoring ý Sources and PDF

Most desktop processors, such as the K6 and Pentium, are equipped with performance monitoring counters. These counters permit processor performance parameters to be monitored and measured. Such information is useful for performance tuning. Current techniques typically use two counters that simultaneously record the occurrence of pre-specified events. When one of the counters overflows, counting stops and an interrupt is generated. Post-processing software is used to analyze the gathered data.

In this article, weýll describe a new technique for gathering and analyzing performance data with a microprocessor or microcontroller. The technique avoids the limitations imposed by fixed-size counters, which eventually overflow. This method is less intrusive and suitable for monitoring a wide range of performance parameters.

Also, a performance improving DRAM interface buffer is described, as well as the monitoring technique used to examine and tune its operation.

PERFORMANCE MONITORING COUNTERS

Two large counters, about 40 bits or more, are usually provided for event counting. These counters can be read and written from within the register address space. The counters can be configured to measure such parameters as the number of data reads that hit in the cache. In this case, the second counter can be programmed to record the number of data reads performed. The ratio of these two numbers gives the cache hit rate for reads.

When one of the counters reaches its limit, the overflow signal can be used to stop all counting and generate an interrupt. The software interrupt handler then records the counter values and completes post data processing and any other support work necessary.

The size of the counters is important. The larger the counter, the less frequently an interrupt is generated. Interrupts are undesirable because they intrude on normal processor operation. A larger counter also results in greater data averaging. Any temporary fluctuation in the cache hit rate is not observed. This may or may not be what is required.

Before performance monitoring can be accomplished, an interrupt handler must be installed to deal with counter overflow. Of course, overflow can be avoided by the use of extremely large counters. But, such a technique may be expensive to implement, unreliable, or fail to produce the desired statistical analysis.

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