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MONITORING YOUR MICRO

by Daniel Mann & Jim Magro

Start ý Data Gathering ý DRAM Memory Interface Buffer ý Write Buffer "Hit" Monitoring ý Sources and PDF

DRAM MEMORY INTERFACE BUFFER

Microcontrollers often incorporate memory interface circuitry, which eliminates the glue logic required with most microprocessor-based systems. AMDýs Embedded Processor Division is currently developing an advanced memory interface technology. The interface will include two buffering techniques (the write and read buffer) that optimize the effects of DRAM performance on overall system performance.

The write buffer provides a mechanism for writes to DRAM achieved with a zero memory wait-state. For those of you who are unfamiliar with a memory wait-state, it is the number of additional clock cycles required to access a memory resource. Fast SRAM has fewer wait-states than slower DRAM.

The write buffer effectively de-couples write activity from incurring the normal DRAM latency penalty. This, in effect, also allows the DRAM to remain free to satisfy a higher demand, such as a data read request. In addition, the write buffer provides write merge and write collapse functions. These techniques enable better usage of the bufferýs limited storage and reduce the total number of transactions to DRAM. Data read merging is additionally supported to maintain data coherency.

The read buffer provides storage for eight words (32 bits) read from DRAM. The memory is divided into four word blocks known as cache lines. When the processor requires a value currently held in memory, the whole cache line (or block of memory) is read into the processor. Consequently, the read buffer is better described as consisting of two cache lines. The read buffer supports an optional read-ahead function, which ensures the prefetching of the cache line, where the address immediately follows the requested cache line. This feature is provided in anticipation of future accesses to the pre-etched memory block (spatial locality).

The performance of the memory interface buffer is monitored by two Addie units. Through a multiplexer, each Addie can be configured to monitor a range of different performance parameters. The following sections describe some of these parameters and show how the performance data obtained can be used to further optimize and analyze system performance.

PERFORMANCE-ENHANCING FEATURES

The write buffer can hold up to 32 words (4 bytes per word) of data waiting to be sent to the system DRAM. Each write request results in a snoop of the write buffer contents. The snoop is used to determine if the data associated with the write request already exists in the buffer. The term "associated" refers to the address of the new data, matching up to an address tagged to data waiting for transfer to DRAM. This feature allows write data to be merged (or collapsed) with data that already exists in the write buffer.

Merging data writes results in a reduced number of overall writes to DRAM. It also results in more efficient use of the write buffer storage.

The write buffer supports read merging. Read merging occurs when a read request "hits" (is associated with) a word that currently exists in the write buffer. In such a case, the data returned from DRAM is replaced, or merged, with existing bytes from the write buffer (see Figure 5).

Figure 5ýHereýs a memory interface buffer. The data returned from DRAM is replaced or merged with existing bytes from the write buffer.

Without the snooping capability and read merge logic, the entire contents of the write buffer would have to be flushed prior to any read cycle. This would be required to prevent reading old data from DRAM that is about to be updated by data held in the write buffer. Snooping results in less overhead, while maintaining data coherency. With some write buffers, snooping is merely used to determine if flushing is required. A performance advantage is achieved by activating read merge logic when snooping detects a write buffer hit.

The write buffer also supports a read-around-write feature. This allows read requests to DRAM to occur ahead of (or around) write requests waiting in the write buffer. Allowing read requests to be processed without additional delays reduces processor stalling and, in turn, improves system performance.

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