|
by Daniel
Mann & Jim
Magro
Start ý Data
Gathering ý DRAM Memory Interface Buffer
ý Write Buffer "Hit" Monitoring
ý Sources and PDF
SOURCES and PDF
Download
the PDF of this Article. 
Daniel Mann is on the Technical Staff
of AMDýs Embedded Processor Division. He has worked extensively on
developing on-chip technology supporting microprocessor software development
and performance measurement. He is currently working on Box development.
You can contact him at daniel.mann@amd.com.
Jim Magro is on the Technical Staff
of AMDýs Microprocessor Products Division. He has worked on various
DRAM controller designs, which include the AMD Elan SC520 SDRAM controller,
read buffer, and write buffer. He is currently developing the high-performance
Double Data Rate (DDR) DRAM controller in the AMD-761 chipset for
the AMD Athlon processor. You can contact him at jim.magro@amd.com.
REFERENCE
[1] A. J. Miller, A.W. Brown, P. Mars,
A Study of an Output Interface for a Digital Stochastic Computers,
Int. J. Electronics, 1974, Vol. 37, No. 5, 637ý655.
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