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CHARMING ADDERS

IMPLEMENTING AN ADDER IN AN FPGA
by Ingo Cyliax

Start ý Implementing ý Adder Architecture ý Lessons Learned ý Sources and PDF

Designing with FPGAs is a lot like designing with other digital components. You have some idea of what functions you would like to implement in your design, and the FPGA provides the basic building blocks to implement these. As you recall, FPGAs are made up of an array of logic blocks wired together with routing resources. Except for some functions, the routing facilities are only used to connect the blocks. This month, Iým going to show you some examples of how familiar structures are implemented in FPGA logic blocks.

One of the most common digital functional blocks is the adder, which is used in counters and arithmetic functions. The adder is a structure that is difficult to implement efficiently. The truth table for a full adder, an adder that has a carry input and carry output, is shown in Table 1. Youýll need the C_IN and C_OUT signals to cascade adders to implement adders for larger word sizes.

A simple 1-bit full adder can be constructed with the following functions:

Sum = A XOR B XOR C_IN

C_OUT = (A ý B) + (A ý C_IN) + (B ý C_IN)

Figure 1ýThe logic to implement a native full adder. It takes the carry input, adds it with the two operands (A and B), and generates the outputýs sum and carry out.

To build a 16-bit adder, you simply chain 16 adders together (see Figure 1) by wiring the C_OUT to the C_IN of the next stage (see Figure 2). This particular design also has input and output registers to hold values.

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