Answer1

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Problem 2—A 1GHz clock signal is distributed to other parts of the circuit as shown below, using a 1mm copper trace on a low loss substrate (microstrip line No 1). The trace is split into four 1mm traces so that the clock signal can be delivered to four subsystems. Is this a good design?

If the amplitude of the clock signal is 5V into port 1, what would be the voltage seen at the terminations 2 through 5? Assume that the signal travels along the traces without dispersion or loss, and that all the traces are terminated in matched loads. Disregard any inductance or capacitance at the junction.

Answer:

This is an example of a bad design. Four transmission lines (2-5), each with impedance Z₀ are connected to a transmission line (1) that also has impedance Z₀. In effect, the signal travelling down line (1) arrives at a discontinuity with a shunt connection of 4 lines; it effectively sees a load with impedance of 0.25 Z₀.

The reflection coefficient at this point will be

G = Z_L – Z₀
Z_L + Z₀ = 0.25 Z₀ – Z₀
0.25 Z₀ + Z₀ = – 3
5

At the junction the voltage is equal to the sum of incident and reflected voltages, or

V = V⁺ + V^– = V⁺ + G V⁺ = 2
5 V⁺

Since the connection is shunt, this will be the voltage wave amplitude in each of the attached lines. So, if the original amplitude of clock signal was 5V, only 2V will be seen at the subsystems to which the clock signal was sent.

Contributor: Michal Okoniewski

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