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by George Novacek
Start ý Data
Bus Systems ý Timing is the Secret ý
ARINC 429 ý CSDB
and ASCB ý MIL-STD-1553B ý ARINC
629 and Beyond ý ARINC 429 Implementation
ý Data Format ý Wrap
Up ý Sources and PDF
ARINC 429 IMPLEMENTATION
One hundred kilobits per second throughput
aside, this slug of a protocol is still the most popular on transport
aircraft, so letýs take a closer look at its implementation. Its specification
is 520 pages thick, so all I can do with this article is merely explain
the fundamental aspects of the inner workings. [3]
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| Figure 2ýHereýs the definition
of input and output voltage levels for ARINC 429 data bus. |
The signal is in bipolar,
return-to-zero (RZ) format (see Figures 2 and 3). It is tri-state,
with the defined levels 1, 0, and null. The transmitter output voltage
swing is ± 10 V nominally, at 12.5 or 100 kb/s. Rise and fall
times are specified to be 10 ý 5 ýs for the slow and 1.5 ±
0.5 ýs for the fast format. The rise and fall times specification
makes the pulses trapezoid in shape, and with their return to zero
characteristic, resembling a sinusoid. This results in a significantly
lower harmonic content (less radiated interference) than you would
get from a rectangular wave shape, such as RS-232.
 |
| Figure 3ýThis timing diagram
of ARINC 429 data bus shows a bipolar return-to-zero (RZ) format. |
The hardware interface is simple to implement
with discrete components, as shown in Figure 4, and the protocol timing
functions provided by a microprocessor. To create the transmitter,
you need only a couple of buffers to drive the lines in bipolar fashion.
For slow speed, many small monolithic audio amplifiers will do. For
the fast mode, current buffers such as LH0002 can be used. The receiver
is more complicated, involving a differential amplifier feeding several
window comparators to decode ones (Line A HI), zeros (Line B HI),
and nulls. The transmitter output resistance Ro should
be 75 ohm. Resistance Rs split between two resistors in
series with the buffers provides the necessary adjustment of the usually
very low-impedance buffer outputs. The receiver differential input
resistance should be greater than 12 kilohm, with >12 kilohm between
either input and ground. The linesý and inputsý parasitic capacitances
should be kept below 50 pF. Up to 20 receivers can be hung onto one
transmission line.
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(Click
to enlarge)
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| Figure 4ýCheck out the hardware
implementation of ARINC 429 data bus link. |
Figure 5 is an example of a different
implementation of the receiver. It is simple and robust, built with
two optocouplers and a couple of LEDs. The input resistance is less
than the recommended 12 kilohm, but the protocol is robust and capable
of handling this type of interface. The advantage of the circuit is
that it is simple and provides excellent line isolation. The LEDs
are needed instead of regular diodes to provide the necessary null
voltage window.
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| Figure 5ýThe receiver can be
also built with optocouplers and LEDs to provide the required
null threshold. |
If your budget isnýt severely restricted,
I highly recommend that you opt for an interface chip, such as Holtýs
HI8282, instead of building your own hardware. The interface chip
costs around $40 and contains one complete transmitter and two receivers
with all the necessary functions, voltage level shifters, line drivers,
and serial-to-parallel converters. The block diagrams of the receivers
and the transmitter are shown in Figures 6 and 7. ARINC 429 transmitter
assembles data in 32-bit words and the message packets are transmitted
at a repetition (or update) rate of, usually, 3 to 5 Hz. Every receiver
needs to listen to the chatter and determine whether the message is
intended for it or some other user. Consequently, this is resource-intensive
processing. Supporting your own hardware by generating the properly
timed pulse train for one transmitter and decoding the incoming chatter
from one receiver, both at the slow data rate, can use most of the
68HC11 microcontrollerýs processing power.
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| Figure 6ýHoltýs HI 8282 receiver
section is shown as a block diagram. |
The Holt chip unloads this overhead from
the microprocessor. It interfaces directly with the communications
lines and accepts data from and sends data to the microprocessor in
parallel fashion in 16-bit chunks. By taking care of the timing and
all serial data processing, it not only saves a lot of processing
resources, but also eliminates software development and certification
of potentially critical functions.
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| Figure 7ý Hereýs a block diagram
of Holtýs HI 8282 transmitter section. |
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