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THE ETHERNET DEVELOPMENT BOARD

Part 2: The Software and Firmware Exposed
by Fred Eady

Start ý The Basics ý Registers ý Bus Interface Registers ý Status and Control Registers ý InitChip ý Initiate Transmit Registers ý Address Filter Registers ý Receive and Transmit Frame Locations ý CS8900A-CQ Transmit and Receive Operations ý The Next Read ý Broadcast ý ARP ý No Cheating ý Tiger Woodsý Putter ý Whatýs the Point? ý And It Programs, Too! ý Sources and PDF

INITCHIP

Continuing our observation of InitChip, it is obvious that the ether will be 10BaseT (LINECTL_10BASET), and the CS8900A-CQ will pump encoded bits onto the ether in full duplex mode (TESTCTL_FDX).

References to the status and control registers can be found throughout the Ethernet development board code because their job is to report the status of transmitted and received frames. Status and control register activity can also exist in situations where you need to know how the CS8900A-CQ feels. Listing 7 is the CS8900A-CQ reset sequence.

The reset bit within ppageSelfCTL is set and a 10-ms delay is implemented to allow the CS8900A-CQ to calibrate its on-chip analog circuitry. The ppageSelfCTL RESET bit (SELFCTL_RESET) is a bit that acts once. That is, it is set and cleared automatically by the action it initiates and, thus, can only kick off an operation one time.

While Iým on the subject of the self-control register, the SELFCTL_RESET mask also determines how the link LED will operate. Obviously, you turn on the link LED function with the SELFCTL_RESET mask. After 10 ms, a bit check is made on the INITD bit in the self status register (SELFSTAT_INIT_DONE_BIT). When this bit clears, the global CS8900A-CQ reset is complete.

The last status and control area I will examine here is the bus status register, ppageBusStatus. To gain transmit buffer area, the host must bid for transmit space on the CS8900A-CQ. BUSSTA_RDY4TXNOW_BIT signals the host that the CS8900A-CQ is ready and willing to accept a frame from the host for transmission. The complex coding needed to affect this is shown in Listing 8.

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