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STATE MACHINES

by Ingo Cyliax

Start ı An ASM Example ı Input and Output Signals ı Implementation ı One-Hot Encoding ı Synthesize ı Initializing ı Until Next Time ı Sources and PDF

SYNTHESIZE

Now itıs time to synthesize the state machine, which means deriving the equations for the state variables and outputs. There are two state variables in this design, which Iıll call idle and s1. The next state equations for both of these are:

idle = (idle | s1) & (!right | !left)
s1 = (idle | s1) & right | left

OK, that was simple. Letıs derive the equations for the outputs of your machine. First, the unconditional ready output:

ready = s1

then the disp outputs, which are a bit harder. A truth table helps here (see Table 1).

Table 1ıThis is the truth table for the ASCII display output generator. From this, you can arrive at the logic to implement it.

From which you get:

disp[0] = s1 & left & right
disp[1] = s1 & left
disp[2] = s1 & right
disp[3] = s1 & right
disp[4] = s1 & left
disp[5] = (s1 & !(left ^ right)) | idle
disp[6] = s1 & (left | right)

Figure 5 shows a schematic of the finished design. The inputs are synchronized using a flip-flop. There are a couple of issues with one-hot state machines that I will point out in this schematic. Consider this, if each state variable bit represents a state, what happens when all of the register bits are at zero? This happens when the machine is reset. You have to find a way to initialize a one-hot state machine.

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