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STATE MACHINES

by Ingo Cyliax

Start ý An ASM Example ý Input and Output Signals ý Implementation ý One-Hot Encoding ý Synthesize ý Initializing ý Until Next Time ý Sources and PDF

INITIALIZING

One way to initialize a one-hot state machine is to use a preset signal on the state that represents the starting state of your machine, while the rest of the state bits use reset signals. This works, of course, but it wonýt if none of the signals reset the machine. For example, an FPGA will power up with all of the registers set to zero. Youýd have to provide an external reset signal to get things started. Obviously this is not a robust design.

Another strategy is to recognize the null state and cause a transition to the start state. This scheme will cause a glitch in the first clock tick when the state is still null. You also have to make sure that the outputs are decoded properly for the null state. Itýs not a clean design.

A better solution is to invert the input and output sense of the register that represents the start state. This way, if all of the registers get reset to a zero value, the encoding for the start state will be true (i.e., zero means true). This is why there are inverters on one of the registers in the schematic, representing the idle state.

By the way, inverters are free in FPGAs; they get absorbed into the equations used.

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