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STATE MACHINES

by Ingo Cyliax

Start ı An ASM Example ı Input and Output Signals ı Implementation ı One-Hot Encoding ı Synthesize ı Initializing ı Until Next Time ı Sources and PDF

UNTIL NEXT TIME

There are some rules you will need to follow in order to reduce the number of pitfalls youıll encounter when designing synchronous state machines or other synchronous circuits.

First, use only synchronous inputs to control state transitions. By having inputs flip-flop depending on asynchronous signals, youıre asking for trouble. This introduces the chance for metastability and manifests itself in unpredictable ways.

The design might work for days in the lab or even a long time in the field, but eventually the odds wonıt be in your favor, and it will fail. And worse, the situation is not repeatable. Itıs easy to synchronize an input by adding a flip-flop to it. There are input flip-flops in almost all of the FPGA technologies available today. By adding the flip-flop to an asynchronous signal, youıll make sure that whatever metastable event happens to the input register, it will have settled before reaching the state machine next state generator.

Next, use a single clock per domain. Each signal that has to traverse clock domains is an asynchronous signal. It helps to move modules in different clock domains to different schematic pages or HDL modules. If possible, donıt design with multiple clock domains.

Also, donıt gate the clock. Adding a gate to the clock signal will add clock skew. Many FPGAs have flip-flops with clock enable inputs that are implemented so as not to add latency to the clock signal. Use the architectural clock enable, and make sure it is driven by a synchronous signal. Basically, the clock should go straight to all of the clocked elements in a single clock domain. Use global (low skew) clock buffers to distribute the clock in an FPGA. And, donıt use the clock signal itself in any of your logic.

Finally, use top down design for designing state machines. This means you should work out the design specification, separate the architecture (data path) from the control, assign the encoding of the signals, and then optimize and derive the equations for the implementation.

Granted, this design is simple. It only has two states and doesnıt do anything interesting. It does, however, illustrate the basic design methodology that can be used to design state machines in FPGAs using one-hot state machine encoding and ASMs.

Next time, Iıll look at a more complex design that uses a data path in addition to a control.

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