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MANUFACTURING TESTING

by George Martin

Start ı The Problem ı A Possible Solution ı Test Setup ı POP Quiz ı Final Exam ı Sources and PDF

A POSSIBLE SOLUTION

The design uses a Motorola Coldfire 5602e. So I hit the Motorola site (http://e-www.motorola.com/webapp/sps/library/prod_lib.jsp) and selected the specific device. There I found the following.

"The MCF5206 integrated microprocessor combines a ColdFire processor core with several peripheral functions such as a DRAM controller, timers, parallel and serial interfaces, and system integration. Designed for embedded control applications, the ColdFire core delivers enhanced performance while maintaining low system costs. To speed program execution, the on-chip instruction cache and SRAM provide single-cycle access to critical code and data. The MCF5206 processor greatly reduces the time required for system design and implementation by packaging common system functions on-chip and providing glueless interfaces to 8-, 16-, and 32-bit DRAM, SRAM, ROM and I/O devices."

You can also take a look at the Motorola Product Brief for this processor in PDF format (download PDF).

The specific design Iım going to discuss has DRAM, flash memory and battery-backed-up SRAM (BBSRAM), and the memory devices. Peripherals range from simple (such as a latch to hold LED drive signals) to complex (an HDLC controller with DRAM memory attached to the back side of that controller). I just happened to have defective boards that have problems in each of these areas.

I wanted to load code that would execute test routines to exercise all the signals lines associated with each of these devices. Clearly, if all of the memory is operating, code to exercise the HDLC controller would be just a matter of design, code, and test. But, what happens when the DRAM is not functioning? How do you load any code?

The ı5206 fetches vectors from address 0x0000 at power on reset. So, you need memory located at that address to load the code you need to execute. Also, that memory type needs to be RAM so that you can load code into that memory. In production, the flash memory is located at 0x000, and vectors and code are fetched from the flash memory.

The chip selects are controlled by configuration registers. Powerup defaults for these registers are detailed in the processorıs users manual. The processor starts up after a power on reset, and the flash memory is connected to the boot device chip select pin. The powerup default settings are such that data can be fetched using an 8-bit wide data bus with maximum wait states.

Using the BDM pod, you can reset the processor and change the contents of the configuration registers such that the boot device is pointing to either BBSRAM or DRAM. If the BBSRAM or DRAM is working, you can load and execute code. If either the BBSRAM or DRAM is in trouble, you can use the other. If both are in trouble, you could program the flash memory and attempt to execute code from it on powerup. Unfortunately, thatıs not a workable solution in my case because the flash memory devices are soldered to the board.

The final option would be to map any internal SRAM to 0x0000. The users manual for the MCF5206e section 5 states that you can do this, but you need to set the SRAM base address registers using supervisors instructions. It also says that the BDM device can perform these operations. I donıt know if all BDM modules will support this operation, but perhaps this is a feature you should consider when deciding which BDM device is best to purchase. Spending an extra $1000 for a great BDM, one that would permit using internal SRAM as boot device, would get you a gold star. If only management understood how great we are.

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