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Manufacturing Testing


Circuit Cellar Online
THE MAGAZINE FOR COMPUTER APPLICATIONS
Circuit Cellar Online offers articles illustrating creative solutions
and unique applications through complete projects, practical
tutorials, and useful design techniques.

MANUFACTURING TESTING

Lessons from the Trenches

by George Martin

Start ý The Problem ý A Possible Solution ý Test Setup ý POP Quiz ý Final Exam ý Sources and PDF

POP QUIZ

If you look closer at how the DRAM is connected to the micro, youýll see the control signals CAS[0,1,2,3], RAS[0,1], and DRAMW. All are active low, but thatýs not significant for this discussion. And of course, there are the address and data lines. On different micros youýll find different detail connections, but similar DRAM devices need the same signals presented to them so the end results should apply to all.

A normal read transfer goes something like this:

  • Row addresses valid
  • RAS goes low (active)
  • Column addresses valid
  • CAS goes low (active)
  • Data is valid

 

And, a write transfer is much the same as the read transfer except DRAMW is active (low). Physical address lines from the inter core of the micro are mapped onto the DRAM devices. On the MCF5206e, Address [9ý27] can be used to drive the DRAM devices. Using 4Mx8 and 1Mx8 devices, CPU A[10] is connected to DRAM A[0]. And so on, up to CPU A[21] connected to DRAM A[10]. A good test would be to present an address pattern that places all addresses low, then raises one address bit at a time. This would permit you to go in with a scope, trigger on the start of a DRAM cycle, and look at each address line for a valid signal. In my example, a walking 1 from CPU address A[0] to A[20] would do the trick. Each micro will have a different mapping but the technique is much the same.

Again, on the high-performance devices, the data bus can be wired in several ways to the DRAM. I would just cycle a 1 pattern on each of the data bus lines, but keep in mind your specific wiring.

DRAMs have burst transfers in different page modes. If you have a DRAM that passes simple tests but does not pass a burst-mode testýwell, letýs leave that for another day. I would suspect thatýs a power supply/decoupling problem.

One important point to remember is that these micros have instruction and data caching. Be sure that you have turned these features off! If they are enabled, you are only testing the cache and not the external devices.

 

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