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SPEEDING UP YOUR BACKPLANE

Designing for High Performance with PSI
by Michael Moore

Start ý A New Approach ý Current Standards ý The Next Generation ý Implementation Using PSI ý SERDES Requirements ý Integrated CDR and Encoding Functionality ý Jitter and Eye Diagrams ý High-Speed Memory ý Backplane Applications ý InfiniBand Applications ý Port-Side Applications ý Software Support ý Advantages of Optical Solutions ý Application Example ý Wrap-Up ý Sources and PDF

Todayýs designers of high-speed communications systems face many challenges, some of which are particularly noticeable in the design of backplanes. Traditional parallel-bus backplanes have served well in the past, but as bandwidth requirements continually increase, these parallel buses become the limiting factor in the design. Traditionally, shared-bus topologies such as PCI or VME have been used in backplane applications. However, these are limited in terms of scalability, bandwidth, and distance. Even PCI-X, the latest flavor of PCI, is expected to be limited to operation of just over 1 GBps.

These limitations become obvious in high-speed backplanes found in systems like network routers or switches or enterprise storage devices. These devices need to be scalable and should not suffer from the bandwidth or distance limitations of parallel backplanes. Reliability is a problem with shared buses, because a failure in any single pin or connection will cause the whole interface to fail. This is especially relevant with todayýs high-reliability requirements for data centers, internet business servers, and peripherals.

A new paradigm is required to enable both intraboard and interboard communication at high speed, with lower I/O count and greater reliability.

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