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SPEEDING UP YOUR BACKPLANE

Designing for High Performance with PSI
by Michael Moore

Start ý A New Approach ý Current Standards ý The Next Generation ý Implementation Using PSI ý SERDES Requirements ý Integrated CDR and Encoding Functionality ý Jitter and Eye Diagrams ý High-Speed Memory ý Backplane Applications ý InfiniBand Applications ý Port-Side Applications ý Software Support ý Advantages of Optical Solutions ý Application Example ý Wrap-Up ý Sources and PDF

IMPLEMENTATION USING PSI

To implement these interfaces with the serial transceiver, programmable logic offers the best choice of flexibility, performance, and time to market. The Cypress PSI device integrates the worldýs biggest complex programmable logic device (CPLD) with Cypressýs industry leading serial transceivers. The PSI is available in two versions. The frequency-agile version has multiple channels operating from 200 Mbps to 1.5 Gbps. The high-speed version has a 2.5-Gbps SONET/SDH transceiver with Bellcore jitter compliance in one package.

Figure 1ýThe high-speed PSI combines 2.5-Gbps SONET-compliant SERDES with programmable logic and plenty of memory for communications.

The high-speed PSI is perfectly suited for both port and backplane solutions in typical linecard applications (see Figure 1). The smooth integration of SERDES, CDR, and programmable logic enables you to quickly create custom solutions and concentrate on the parallel side of their interface. It has low-power consumption (2.8 W) and supports software simulation for both logic and the PHY.

Figure 2ýThe frequency-agile PSI combines four to eight serial channels, each operating from 0.2 to 1.5 Gbps with integrated 8B/10B encoding/decoding and programmable logic with a lot of memory.

The frequency-agile PSI designed for varies frequencies is well-suited to backplane and port-side applications, supporting standards such as Gigabit Ethernet, FibreChannel, SMPTE, HDTV, and so forth (see Figure 2). It offers combined serial bandwidth from 200 Mbps to 12 Gbps on a single device (see Table 1).

The Cypress Delta39K CPLD architecture provides the programmable functionality for the PSI devices. This is a high-density CPLD that offers significant advantages when you need the higher gate count of FPGAs but want to retain the ease-of-use of CPLDs. The Delta39K architecture offers rich logic and memory resources (>240 Kb of RAM on the Delta39K100), a flexible timing model with abundant routing resources, in-system re-programmability, and many other features. These features enable fast time to market, low costs for prototyping, and the ability to add to designs or change pinouts at any stage in the design cycle. This device integrates all of Cypressýs core competencies in high-speed memory, timing products, and programmable logic in one package.

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