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SPEEDING UP YOUR BACKPLANE

Designing for High Performance with PSI
by Michael Moore

Start ý A New Approach ý Current Standards ý The Next Generation ý Implementation Using PSI ý SERDES Requirements ý Integrated CDR and Encoding Functionality ý Jitter and Eye Diagrams ý High-Speed Memory ý Backplane Applications ý InfiniBand Applications ý Port-Side Applications ý Software Support ý Advantages of Optical Solutions ý Application Example ý Wrap-Up ý Sources and PDF

HIGH-SPEED MEMORY

The PSI device offers abundant high-speed memory (>480 Kb of RAM on the 200K gate devices), including integrated control logic. This control logic consists of dual-port arbitration and FIFO flag logic integrated directly on silicon, ensuring that the memory operates at Fmax. This also saves you from having to implement the control logic in the programmable section, thereby saving gates.

The programmable section of the PSI (based on the Delta39K CPLD architecture) offers a flexible timing model with abundant routing resources, ensuring ease of integration of your design on the PSI. This enables fast time to market, low costs for prototyping, and the ability to add to designs or change pinouts at any stage in the design cycle.

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