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CORE WAR

by Tom Cantrell

Start ı Guns Blazing ı The Curtain Rises ı RISC 101 ı 32 Bits orBust ı There's the Bell • Sources and PDF

RISC 101

Of the many ironies Iıve observed over the years, the RISC revolution surely ranks high on the list. It wasnıt long after the first crop of grad students spun their early ı80s mini-me CPUs that the reduced chips started to put on weight. Yes, todayıs super-scalar, super-pipeline, multi-issue, out-of-order, branch-predicting, speculative, vectorizing, long-instruction word wunderchips are neat, but isnıt it a stretch to call them reduced?

The main culprit? Blame the march of silicon and lust for desktop performance bragging rights for taking the turn on the byway to bloat.

But, for a soft-core CPU running in an FPGA, size does matter and smaller is better. First, FPGA transistors (i.e., area for a given logic function) cost a lot more than hardwired chips. Second, although FPGAs can crank a decent clock rate out of a simple data path, the complicated control logic associated with super-duper features ends up chewing valuable interconnect resources and slowing the whole chip down. Finally (and fundamental to the whole SoC concept) is the presumption that youıve got other neat stuff besides the CPU core that youıd like to fit on the chip.

So, dust off that beaten-up copy by Hennessy and Patterson, the Old Testament of RISC, and youıll find something close to MicroBlaze. [2] In light of all thatıs transpired since, maybe I should call MicroBlaze a retro-RISC. Letıs take a closer look, and I think youıll see what I mean.

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