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CORE WAR

by Tom Cantrell

Start ı Guns Blazing ı The Curtain Rises ı RISC 101 ı 32 Bits orBust ı There's the Bell • Sources and PDF

32-BITS OR BUST

MicroBlaze starts with a 32-bit ALU and general-purpose 32 ı 32 register file. Register GR0 is hardwired to zero, but otherwise any register can be used for any purpose, although the C compiler adopts certain conventions (see Table 1). In addition, there are two special-purpose registers, a program counter (PC), and machine status register (MSR). The latter is normally accessed as a byproduct of instruction execution (e.g., an arithmetic operation affects the carry flag in the MSR), but can also be accessed with move to and from special register instructions (MTS and MFS).

There are a whopping two, count ıem two, instruction formats, type A and type B (see Table 2). The first is the classic three-operand register-register format (destination_reg = source_reg1 op source_reg2), and the second handles register-immediate operations (destination_reg = source_reg1 op immediate).

As you can see from the second format, only 16-bits of immediate data are accommodated directly. Larger immediates are always a hassle for machines with same size instruction and data because thereıs no room in the instruction for both an opcode and full-size immediate.

To overcome the problem, both NIOS and MicroBlaze use a special immediate instruction (IMM) in which 16 bits of immediate data are loaded into a temporary register for use by the next instruction. By default, a type B instruction simply sign-extends its 16-bit immediate data to 32-bits. However, if it follows an IMM instruction, the upper 16-bits of immediate data are taken from the temporary register and concatenated with the lower 16-bits contained in the instruction to form a 32-bit immediate.

I assume that interrupts and exceptions are locked out across the IMM and the type B instruction pair. In any case, if the instruction following an IMM instruction isnıt type B, the 16-bits in the temporary register are no longer valid or, as stated in the documentation, they "become useless."

Otherwise, even a mere 6-bits of opcode overstate the complexity of the instruction set (see Table 3). Thanks to the consistent use of generic instruction modifiers, in essence, MicroBlaze has just the bare minimum of a couple dozen or so instructions needed to get anything done.

The absence or presence of an immediate (I) modifier tacked onto the instruction designates register-register or register-immediate operation (i.e., type A or B), respectively. Practically every instruction can exploit this option.

Furthermore, ADD and SUB instructions have their own options relating to the carry bit. The C modifier, as is typically the case, performs the math function with the carry bit as an input. Furthermore, the K option keeps the carry bit unchanged.

So, although there are indeed eight unique opcodes for addition, itıs conceptually just ADD with I, K, and C modifiers, or combinations thereof.

Similarly, besides the I option, branch instructions also have their own generic modifiers including link (L), absolute (A), and delay (D). The L option stores the PC in a general-purpose register (i.e., turns the branch into a subroutine call). A designates absolute, rather than PC- relative, target address. Finally, D specifies whether or not the instruction in the delay slot following the branch will be executed. The latter is a nice touch because it allows the compiler to exploit the delay slot if it can schedule a useful instruction, but it doesnıt have to insert a code- bloating delay slot NOP if it canıt.

Along the same line, load and store instructions have byte, half-word, and word modifiers along with the immediate option. Half- and full-word operands must be memory-aligned. This is a pure RISC machineıthe only operations that touch memory are load and store.

There is a multiply instruction (MUL) that, according to the documentation, performs a 32 ı 32-bit multiply but only stores the lower 32 bits of the result. I wonder if itıs wise to burden the basic architecture with the presumption of a multiplier. There is no divide instruction, but the compiler incorporates a procedure to handle it in software. I think the ideal solution would call for the specific choice of numeric functions and their capabilities to be at the userıs discretion, with the software tools transparently adapting to the chosen configuration.

Did you notice that there are right shift instructions but no left shifts? Unless itıs a typo, I imagine left shifts are accomplished another way (i.e., by adding a register to itself using the K and C options to differentiate between an arithmetic and logical shift). Indeed, if the aforementioned multiplier is single cycle, thatıs the equivalent of a barrel left-shifter (i.e., multiply by an immediate power of two).

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