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HELPING THE ENVIRONMENT:

EMBEDDED SOFTWARE DEVELOPMENT
by Daniel Mann

Start ý Host-to-Target Connection ý Bringing Down Tool Costs ý Hardware Connection ý Supported Functions ý Trace Cache Data Compression ý Future Tool Methodologies ý Sources and PDF

HOST-TO-TARGET CONNECTION

Generally, and certainly at the early stages of software development, embedded (target) processors are controlled from remote (host) platforms. These remote machines are said to host the debug and development tools.

The method used to connect the target and host machine is a primary concern for any embedded project. A number of techniques have been used to achieve this connection. ROM monitors typically use a UART and support software located in the target systemýs memory. Using an ICE solves the problem because the target is connected via the ICE umbilical.

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An ideal strategy would use an on-chip dedicated link for all communication with the target. This arrangement greatly simplifies the connection problem. This development port should support high communication speedsýmuch faster than a UART. The port should support target bring-up, as well as kernel-mode debugging, application-mode debugging, and operating system communication needs.

WHAT IS JTAG?

Manufacturers of high-tech electronic products formed the Joint Test Action Group (JTAG) to develop a boundary-scan testing standard. The intent was to enable testing of board interconnections without the need for physical probing. For more information, see Jeff Bachiochiýs article "JTAGýWorking with CoolPLD" in Circuit Cellar 104.

Clocking the test clock (TCK) input pin moves the data along the scan cells making up the test register (see Figure 1). Test cells can be connected to input/output pins or other key internal test points. The test register is also commonly known as the scan path.

Figure 1ýThe boundary-scan test (BST) methodology is based on a test access port (TAP) that can be used to serially clock test data into a chip via the test data input (TDI) pin.

The test data output (TDO) pin serially clocks out the test register stream as data is clocked in. The fourth pin, known as the test mode select (TMS) is an input pin used to control the state transitions of the port control logic. By clocking in 0 or 1 on the TMS pin, the action taken by the controller can be directed. For example, the state of the chipýs input pins can be sampled or different scan paths can be selected.

Conventional microprocessor testing, based on JTAG technology, involves serially clocking test data into selected scan paths within the processor. Test results must also be clocked out serially and scan paths can be long.

Because multiple-scan steps must be carried out for even simple test actions, the process can be time consuming. Even with high JTAG clock rates, scan-intensive technology is too slow for use with software development. However, techniques based on short scan paths and additional hardware-assistance can enable a JTAG port to be used as a communications methodology for a processor port oriented to software development. Such techniques are included under the common title "enhanced JTAG."

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