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THE FPGA TOUR

by Ingo Cyliax

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If youıve followed my articles in Circuit Cellar, you might have noticed my affinity for using field-programmable gate arrays (FPGAs). I was using FPGAs well before they were considered mainstream. More and more people are designing with FPGAs these days, mostly because of the lower costs of the design software required to use them.

We are also seeing more Circuit Cellar articles that use, and are based on, FPGAs. We decided it was time to introduce a new bimonthly column to cover FPGAs and the closely related CPLD. This month, I kick off the column with the first half of a two-part tutorial on what FPGAs and complex programmable logic devices (CPLDs) are.

FPGAs were primarily used to prototype designs for application-specific ICs (ASIC). ASICs require large lead times from design to actual implementation and are produced in large volumes. If a design error was made in a complex design, you would have to spend a lot of money and time to re-spin an ASIC.

FPGAs enable designers to implement designs in hardware for testing and prototyping with much less lead time. The turn-around time for FPGAs is less than a day, and even shorter for small designs. However, because the designs were implemented in CAD tools that are also used to design ASICs, it was generally expensive to get started with FPGAs. Nowadays, the costs for entry-level design tools is low enough for almost anyone to get started using these parts.

In this article, I go over some of the architectural features of FPGAs and CPLDs. Next month, I'll discuss the design flow and techniques. In the months after that, I'll cover many exciting FPGA and CPLD applications.

LETıS GO

FPGAs and CPLDs are in the family of programmable logic devices. The first examples of these devices were programmable logic arrays (PLAs). As you can see in Figure 1, PLAs had two arrays of connections that enabled the designer to program which pins were ANDed and which of the AND terms were ORed together to implement an output function. This procedure was done by burning out little fuse wires on the chip so that only the desired connections remained.

Figure 1ıIn the basic programmable logic array (PLA), you program each array, one for AND and one for OR, by blowing fuseable links to implement logic functions.

After the PLA, the programmable array logic (PAL) shown in Figure 2 was introduced. Here, only the AND terms were programmable, which made the chip less complicated and enabled you to implement wide AND-OR product terms. These chips were popular for implementing decoders.

Figure 2ıIn contrast to a PLA, the programmable array logic (PAL) only has a programmable AND array. This makes the chip less complex (and less expensive), but limits the kinds of expressions that can be implemented efficiently.

One refinement to the PAL was the addition of a programmable register at the output of the AND-OR terms. This made it possible to implement state machines and so the chips are called programmable logic devices (PLD). PLDs have been refined so the output cell can be configured to implement a pass-through function, registered outputs, inverted output, and an internal feedback. One of the most popular PLDs is generically known as the 22V10. The basic design of the 22V10 can be seen in Figure 3.

(click here for figure)

Figure 3ıBy adding an output macro cell, you can turn the PAL into a programmable logic device (PLD). The macro cell contains a flip-flop and a tristate buffer, so the pin that the macro cell is wired to can be a bidirectional I/O pin.

This device is a 22-pin IC that has 10 general-purpose (V) output cells. Any of the 22 pins can be an input to the AND-OR terms and 10 of the pins are wired to the output cells. It's so popular that itıs still manufactured by different vendors in several versions (low-power, high-speed, low-voltage, in-circuit programmable, etc.).