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WHATýS THE LOGIC BEHIND THE DESIGN?

Working with Programmable Logic

by George Martin

Start ý The Search Begins ý Navigating ý Counting the Ways ý Simulation ý Sources and PDF

NAVIGATING

Photo 1 shows the top-level view of the project navigator, which is always visible. Iýve named the project Camera Test Set V.00-11. In the directory, I control each revision by creating a new directory for that revision.

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Photo 1ýThe top-level view of the project navigator is always visible.

The next entry is the M4A5-32/32-10JC. Thatýs the specific device I targeted my application to. You can try different devices and see if they fit and how the design works. If a design fits but is 98% full, you may not want to release that into production. If you select this line in the project sources window, youýll see the steps to compile, fit, and simulate the design.

As you look through the processes shown in Photo 2, you get a feel of the organization and power of this system. Many of these features come from the high-end work station design packages. The maintenance alone for these high-end packages is over $100,000 per year.

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Photo 2ýHere you can see the processes for the device.

Double clicking on the Fit Design process will do just that. A green check indicates successful completion, and a red "x" indicate a warning or error in the process. If youýre accustomed to PLD design, then processes like Constraints Editor will have some meaning to you.

The next file cameratestset.abv is a file automatically created by the software. Do not edit this file because it will be overwritten.

The next file, cameratestset.sch, is the top-level design file. Figure 1 shows the input and output pins and the three functional blocks that make up the design. The clock input is pin 11, the rate selector is pin 36, and the output is pin 17. The inverter and OR gate have instance numbers associated with them. The inverter is I7, and the OR gate is I8. Iýve also defined a divide by 500, divide by 3200, and a Pulse_Extender functional block.

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Figure 1ýInput and output pins and three functional blocks make up the design.

Figure 2 shows the details of the divide by 500 implementation. The program would have permitted this to be an ABEL text page as well as a schematic diagram. A test called Latched Reset is added free form, and I think it adds a lot to the understanding of the design. The basic building blocks consisted of a toggle (T) flip flop with a reset input. But, this reset is asynchronous.

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Figure 2ýHere you can see the details of the divide by 500 implementation.

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