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WHATıS THE LOGIC BEHIND THE DESIGN?

Working with Programmable Logic

by George Martin

Start ı The Search Begins ı Navigating ı Counting the Ways ı Simulation ı Sources and PDF

COUNTING THE WAYS

In the past, Iıve written about PLD design approaches. And, Iıve suggested that youıd better use synchronous design if you want to survive. Well, as I was simulating this design, I counted to 499 and a reset signal appeared and started to reset the flip-flops. As soon as the first was reset, the reset signal went away and the reset process was stopped. So, I added a flip-flop I24 to make the reset synchronous.

This design counts from 0 to 498. Note that thatıs 499 states. Then I22, I25, and I21 decode the state value of 498. The output of I21 goes high and is latched into I24. That latched value is then used to reset all the toggle flip-flops. This reset signal is also the output of the divide by 500 circuit. The output pulse is one clock wide.

The gates I22, I25, and I21 are used to implement the function:

Reset = *Q[0] ı Q[1] ı *Q[2] ı *Q[3] ı Q[4] ı Q[5] ı Q[6] ı Q[7] ı Q[8].

Be certain that the structure of the PDL supports such equations. This is a simple example, and Iım sure the MACH devices can handle a nine-input function. The schematic elements available are limited to four input devices, so you need to create larger input function out of the building blocks. Just donıt get carried away, or itıll be impossible to fit the results into the device.

I needed to stretch the output of divider circuitry. Figure 3 shows the simple piece of logic that captures the input signal. If itıs a one, then it starts a 3-bit counter, which keeps counting until state 0x000 is reached, then it stops counting.

(Click to enlarge)

Figure 3ıThe simple piece of logic that captures the input signal can be seen here.

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