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16-BITS OR BUST

by Tom Cantrell

Start ý Unlikely Source ý Under the Hood ý Nihon-no Micon? ý Sources and PDF

UNDER THE HOOD

The M16C family consists of a variety of parts based on a common architecture. Though the marketing collateral naturally claims the chips are RISC-like, in fact theyýre quite CISCy with 91 semantically rich, variable-length instructions and a dozen-plus addressing modes. Most of the instructions execute in three cycles or less and even MULtiply takes only five cycles.

As odd as it may seem, the architecture strikes me as kind of a cross between a 68k and a Z80. For instance, like the 68K, the eight 16-bit registers are partitioned into data and address roles. And like the Z80, there are two banks of register that are software selectable.

Mini-pickup with a Corvette motor? Actually, I think it sounds weirder than it is. In actual practice, the CISCy nature yields real benefits in terms of code density and, if I may be so blasphemous, ease of assembly-language programming.

The lineup covers a broad range. At the high-end, the M16C/6x and M16C/8x incorporate plenty of memory (the M16C/62 features a whopping 256 KB of ROM or flash memory and 20 KB of RAM), high pin count (e.g., 100 pin) packages with external buses for connecting lots of DRAM, and so on.

However, though impressive and quite capable, I think such high-end 16-bit chips are most vulnerable to the challenge of similarly priced low-end 32-bit chips from outfits like ARM, MIPS, Hitachi, and Motorola.

Though the M16C gives it a good try, chips with 16-bit programmer models invariably stumble up against the 64-KB barrier and, despite oh-so-clever segment and banking schemes, thereýs fundamentally no elegant way around it. If youýre looking at huge programs and lots of pins to hang a bunch of DRAM on, then 32 bits is the way to go.

The brand new M16C/20 is another story (see Photo 1). Hereýs a chip thatýs a good fit with mainstream embedded apps and is even a practical alternative to 8-bit MCUs.

Photo 1ýThough wrapped in an econo-box 56-pin package, the M16C/20 has a 16-bit engine under the hood.

For instance, the ý16C/20 is single-chip only. In other words, all the memory (you can get 32-KB ROM/flash + 1-KB RAM or 48-KB ROM/flash + 2-KB RAM versions) is on-chip. Without the 20ý30+ pins required for external expansion, the chip fits in a tiny 56-pin QFP package and, surprise, even a DIP packageýalbeit, a rather off-the-wall 52-pin SDIP.

I suspect the popularity of the M16C family may have less to do with the architectural whizziness of the CPU core and more to do with the stuff surrounding it. Take a look at Figure 1. You can see the ý16C/20ýs huge selection of peripherals, including six 16-bit timers (plus a watchdog), two UARTs (one also handles clock serial mode) and an 8-channel (up to 13 channels by sacrificing some shared pins) 10-bit ADC.

In case you were wondering, these peripherals arenýt stripped down models by any means. For instance, the timers (see Figure 2) feature a myriad of modes, including event counter, one-shot, pulse-width measurement, and PWM. There are plenty of internal and external clock-source options individually programmable for each timer and a half a dozen pins to work with as well. The UARTs have their own baud-rate generators, allowing completely independent operation without using any of the six timers.

The A/D includes a variety of repeat-sweep modes that cycle automatically through a programmer-defined list of channels. Unlike similar, but simpler, schemes found on other chips, the ý16C/20 can emphasize (i.e., convert more frequently) a particular channel. For instance, the sweep might pay more attention to channel 0 with a sequence like ch.0, ch.1, ch.0, ch.2, ch.0, ch.3, and so on.

Even the parallel I/O is gussied up with bit-by-bit direction setting, nibble-by-nibble pull-up selection, and eight pins offer programmable drive up to 30 mA for directly connecting to LEDs or other high current loads or whatever else might come in handy.

The ý16C/20 also pays attention to details important to real-world embedded apps. For instance, there are two separate oscillators. One delivers the main clock (up to 10 MHz) thatýs used during normal operation and includes a programmable divider chain (1,2,4,8,16), while the other runs off a 32-kHz watch crystal. The neat thing is that you can switch CPU operation to either one via software and disable the unused oscillator to cut power.

For instance, running off the 32-kHz clock and shutting the main clock down, the chip typically consumes as little as 4.0 mA, which is competitive with a typical MCUs all-clocks-off Sleep mode. Both flash memory and ROM versions run at the full 10-MHz speed between a wide 4.0ý5.5-V operating range, while ROM versions can go all the way down to 2.7 V, albeit at a reduced clock rate. RAM contents are retained all the way down to 2.0 V.

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