Norwood, MA (September 5, 2000) -- Analog Devices, Inc announced today the ADSP-21161 SHARC DSP, the newest member of the Super Harvard Architecture (SHARC) family of programmable digital signal processors (DSPs). Capable of 600 million math operations per second (MFLOPs), the ADSP-21161 sets a new level of performance for low-cost SHARC DSPs -- more than three times the performance for comparable models at about the same price. System integration has been optimized for applications such as voice recognition, professional and high-end consumer audio, motor control, automotive entertainment, telephony including mobile telephony, instrumentation, network analysis, network infrastructure and wireless communications. These applications will benefit from the integration of one megabit of memory and ADI's industry-leading multiprocessor interfacing technology.

"The ease-of-use of 32-bit, floating-point DSPs is a tremendous benefit to designers, improving their time to market. A broad portfolio of SHARC DSPs brings these ease-of-use advantages to a wide range of real-time signal processing and multiprocessing applications," said Gerald McGuire, product line director, DSP Division, Analog Devices. "Our road map includes a cost-effective path to 1200 MFLOPS for $5 per unit and a performance-driven path to 10GFLOPS and beyond."

This announcement builds on the continued success of the SHARC family of DSPs. In 1998 Analog Devices was the first major manufacturer to create successful solutions for the low cost, floating-point segment of the of DSP market with a product that was twice as fast as any 32-bit DSP available on the market at the time and more than three times faster than any 32-bit DSP in its price range. This new ADSP-21161 redefines the floating-point market with a further threefold increase in performance, a rich peripheral set and high bandwidth communications. In addition, this announcement will enable designers to quickly and easily build code-compatible, cost-effective, scaleable, single and multiprocessor solutions. Both segments of the SHARC family road map will offer products with a variety of price points, memory sizes and peripherals.

"This newest edition to the SHARC family will open more possibilities for designers to design-in high performance digital signal processing into client-side applications, and should help others reconsider applications they couldn't do before with a single chip," said Will Strauss, president of Forward Concepts. "Analog Devices will certainly maintain customer loyalty with this road map."

The ADSP-21161 -- Breakthroughs in System Integration

The ADSP-21161 is based on the SIMD SHARC core that supports single-instruction, multiple data execution of 32-bit fixed and floating-point arithmetic. It has 1Mbit of on-chip dual-ported memory. This dual ported SRAM has a unique feature that permits the user to customize the mix between the percentage of memory dedicated to instruction and the percentage of memory dedicated to data consistent with the demands of the specific application. The result is a more efficient use of memory and processing power. Fourteen direct memory access (DMA) channels assure fast data transfers that do not steal cycles from the core. System I/O is achieved through two 128-channel synchronous TDM and four I2S serial ports, a 32-bit parallel port that includes a 32-bit SDRAM controller and an SPI interface. Clusters of DSPs can be built using the on-chip multiprocessing interfaces which enable global shared memory within the cluster, and connection of up to six SHARC DSPs and a host without the need to design external circuitry. It also provides hardware and software compatibility with over 70 multiprocessing design tools available from third parties. The 3.3V device is 5.0V-tolerant for I/O.

Tools Support

A wide range of software and hardware development tools supports the ADSP-21161 and subsequent SHARC DSP products. Analog Devices' VisualDSP++ development tools include an optimizing C/C++ compiler, easy-to-use hardware evaluation kits, and in-circuit emulators (ICEs). SHARC emulators provide easier and more cost-effective methods for engineers to develop and optimize SHARC systems, by offering non-intrusive full speed emulation capabilities.

Price and Availability

The ADSP-21161 is manufactured with a state-of-the-art 0.18ý CMOS process. Entry price for the 100 MHz ADSP-21161NKB-100X, 225-BGA (ball grid array) is $35/unit in 1,000 unit volumes. Sampling is planned for Q4, 2000 with full production in mid-2001.

ADI's DSP Strategy

ADI is a leading supplier of digital signal processing solutions, including mixed-signal DSPs, general-purpose DSPs, such as the SHARC family, and embedded DSP solutions that serve secure data, ADSL modems, GSM handsets, Internet access, speech processing and motor control applications. ADI leverages 30 years of high performance analog expertise to develop DSPs that make the design challenge easier. ADI's DSP architectures feature simple, yet powerful programming models and are supported by the White Mountain DSPý brand of high-quality development tools. The DSP Collaborative is a comprehensive network of independent companies and design services consultants serving the ADI DSP community of more than 30,000 software developers. For more information about ADI DSPs visit www.analog.com/dsp.

About Analog Devices

It's no secret that the communications arena has been driving growth in the DSP market in the past year or two. Meanwhile, other markets have started to emerge, and they bring along their own unique requirements. One segment with enormous potential is the consumer and appliance markets, but here performance must play with low cost, low power consumption and high levels of integration. To address this segment, ADI is continuing to develop the low-cost branch of the floating-point Sharc family, this time with the ADSP-21161.

The 21161 follows on the 21065, which came out in the spring of 1998. That older device, selling for $10 in large OEM quantities in the order of 100,000 units, remains the bottom end of the Sharc family. It specs performance of 200 MFLOPS and on-board memory of 0.5M bits. Even though the new entry roughly doubles the price to $20 in OEM quantities, it runs at a 100-MHz core instruction rate and triples raw power to 600 MFLOPS peak (400 MFLOPS sustained). Further, it doubles memory size to 1M bits.

These specs join already existing features in this floating-point chip including easy setup of multiprocessing systems with minimal external circuitry. Its Super Harvard architecture contains four independent buses for dual data fetch, instruction fetch and nonintrusive zero-overhead I/O. In addition, a flexible dual-port RAM allows an engineer to customize the mix of memory devoted to instructions and the amount for data. In this way, says the firm, it's often possible to reduce the number of external memory chips, thereby lowering total system cost. And because this device is code compatible with all other Sharcs, the family continues to expand the upgrade path at both the bottom and the top ends.

Indeed, notes Jerry McGuire, product line director for the DSP Division, the Analog Devices Sharc roadmap calls for the eventual delivery of a part with 1200 MFLOPs yet selling in the $5 range in large volumes. You might start looking for such a device in roughly two years he says. And at the top end is the TigerSharc with its static superscalar architecture.