Geneva, September 29, 2000 -- STMicroelectronics today introduced a highly advanced evolution of the ST10 microcontroller core which employs a new architecture that allows most instructions to be executed in one cycle, more than doubling the execution speed at a given clock speed. In addition, it adds digital signal processor (DSP) instructions optimized for real-time control applications. Called Super10, the new DSP-MCU core brings a significant gain in performance and maintains code compatibility with standard ST10 cores, allowing the re-use of existing software investments in newer, more advanced system-on-chip applications.

The Super10 core primarily targets control applications in hard disk drives, automotive and consumer where DSP algorithms are needed to achieve the required performance. In a hard disk drive, for example, the addition of a true DSP and advanced interrupt handling with fast context switching means that the Super10 core can efficiently support the higher frequency of interrupts required by new concepts such as two-stage head positioning servos, where fine tracking is performed using a microactuator on the head suspension.

Fast response to interrupts is achieved due to two local register banks in the Super10 core which offer zero cycle context switching capability. Moreover, the Super10 core also provides a new interrupt functionality -- the Interrupt Jump Cache -- which allows the interrupt controller to transfer directly to the CPU a 24-bit start address for the service routine without time overhead.

Designed specifically for embedding in system-on-chip solutions, Super10 is a fully synthesizable design for process portability and can be combined with a variety of peripheral and interface IP for fast, effective system-on-chip design. Scalability allows the core to be optimized for specific applications. Currently available for ST's 0.18-micron technology, it can also be implemented with ST's robust, automotive grade embedded Flash memory technology.

The Super10 core can be operated at any speed from zero to 150 MHz and is designed for low power consumption -- 0.2 to 0.5 mW/MHz -- to suit portable applications such as digital still cameras, portable drives and personal digital assistants (PDAs).

Software tools are available from Tasking, which allow easy programming of Super10 cores in C and C++. In addition, application support and training are available. Real-time emulation is provided through ST's partnership with three leading third-party vendors, Nohau, Hitex and Lauterbach, which produce emulators based on ST's bond-out chips. An evaluation board is available from FS Forth and ETI.

Since 1996, ST has sold more than 80 million chips containing an ST10 family core of which more than 11 million also include embedded Flash memory. ST10-based chips are now widely used in volume applications in the hard disk drive and automotive industries. Super10 is a joint development of the industry standard C166/ST10 architecture of STMicroelectronics and Infineon Technologies.

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Although it might appear to be an evolutionary step in an existing product line, the term "evolutionary" doesn't do justice to the improvements that arrive with this third-generation core. The initial ST10 devices, the -16X family, consisted of a pure microcontroller core with some peripherals. The second generation in the -27X family then added DSP functionality, making the part interesting to those who needed both DSP computations as well as some external control abilities, suiting applications such as hard-disk control or tasks in the auto industry.

Now the Super10 (with an official part number in the X300 family) makes some minor peripheral improvements, but the big story is a complete reworking and enhancement of the base architecture. The result is that most instructions now execute in one cycle instead of every two as with the previous generation, thus giving an immediate boost in performance. For instance, you can now execute one FIR tap per CPU cycle. The device combines the power of both a DSP (the same as in the previous generation, with a 16 x 16 multiply-accumulate unit working with a 40-bit register) and an MCU as well as a 5-stage pipeline that executes the instructions. Better showing the boost in power, a chart on the datasheet places the X200 family at roughly 25 MIPS but places the X300 family at 200 MIPS. Not to be forgotten, the device extends its speed/power range, now going from 0-150 MHz with consumption ratings from 0.2 to 0.5 mW/MHz.

The press release states that "most" instructions execute in one cycle. When asked for details, ST10/Super10 design manager Gerard Humeau elaborates that only perhaps 1% or 2% of the instructions don't meet that criteria. Examples he gives include some MAC instructions and the divide -- but that latter instruction can perform in the background while the core starts another instruction, further adding to the device's speed.

And while most instructions need just one cycle, the designers are quite proud of the core's zero-cycle branching capability based on branch-detection and -prediction logic, and this function can run in parallel with other instructions. Another key difference is in interrupt handling. The 2nd generation devices included only one bank of registers. This latest device incorporates two separate register banks that implement zero-cycle context switching.